Abstract: An array substrate includes sub-pixels, gate lines and data lines. The sub-pixels form pixel groups each including the first and second sub-pixels. The first sub-pixel includes a first transistor and a first electrode group including a first pixel electrode and a first commons electrode. The second sub-pixel includes a second transistor and a second electrode group including a second pixel electrode and a second common electrode. The gate lines form gate line groups each including a first gate line and a second gate line. At least part of the data lines each include: first data segments between a i-th column of sub-pixels and a (i+1)th column of sub-pixels, second data segments between a (i?j)-th column of sub-pixels and a (i?j-1)-th column of sub-pixels, and third segments. An overlapping are of the first pixel electrode and first common electrode equals that of the second pixel electrode and second common electrode.

Abstract: A display panel includes an active area and a border-frame area located at a periphery of the active area, the active area includes a plurality of sub-pixels and a plurality of data lines connected to the sub-pixels, and the border-frame area includes a testing area and a bonding area; the testing area includes a plurality of testing units that are arranged periodically in a first direction, each of the testing units includes one or more switching transistors, a first electrode of each of the switching transistors is connected to a testing-signal lead wire, and a second electrode is connected to one of the data lines; the bonding area includes a plurality of bonding units that are arranged periodically in the first direction, each of the bonding units includes one or more bonding pads, and each of the bonding pads is connected to one of the data lines.

Abstract: The present disclosure provides a display panel. The display panel includes a base substrate, a first conductive layer and an active layer that are stacked in sequence. The first conductive layer includes a plurality of gate signal lines. The gate signal line includes a body part and a plurality of additional parts. An orthographic projection of the body part on the base substrate extends along a first direction. The plurality of additional parts are distributed at intervals in the first direction and coupled to a side of the body part in a second direction. The additional part is used to form a gate of a driving transistor. The active layer includes a plurality of active structures disposed corresponding to the plurality of additional parts. Orthographic projections of the plurality of active structures on the base substrate are separated from each other.

Abstract: Disclosed are an array substrate and a display apparatus, a plurality of gate lines are arranged in the first direction in the display area and extend to the bezel area in a second direction; the plurality of data lines are arranged in the second direction in the display area, extend to the second bezel area in the first direction and are arranged around the second display area in the second bezel area; and a plurality of anti-static structures are electrically connected with the plurality of gate lines, the plurality of anti-static structures include a plurality of first anti-static structures located in the first bezel area and a plurality of second anti-static structures located in the second bezel area, at least part of the first anti-static structures extend in the first direction, and at least part of the second anti-static structures extend in a winding direction of the data lines.

Abstract: The present disclosure provides a driving circuit, a driving method and a display device. The driving circuit includes a first pull-down node, a first control circuit and a pull-up node reset circuit; the first control circuit is configured to control to connect the first pull-down node and the first voltage terminal under the control of the first control signal provided by the first control terminal, so that a potential of the first pull-down node is a valid voltage; the pull-up node reset circuit is configured to control to connect the pull-up node and the second voltage terminal when the potential of the first pull-down node is a valid voltage, so as to reset the potential of the pull-up node.

Abstract: Environmentally friendly, sustainable, and high-performance ultralight composite foams are disclosed. The composite foams are prepared from cellulose nanomaterial, polymeric material, and a crosslinking agent. The fabrication process is simple and uses only water. The composite foams exhibit an elastic strain exceeding the values reported for known nanocellulose-based foams with no reinforcement. The foams exhibit a thermal conductivity superior to that of traditional insulating materials and retain structural integrity after burning.

Abstract: The present disclosure provides a display panel. The display panel includes a base substrate, a first conductive layer and an active layer that are stacked in sequence. The first conductive layer includes a plurality of gate signal lines. The gate signal line includes a body part and a plurality of additional parts. An orthographic projection of the body part on the base substrate extends along a first direction. The plurality of additional parts are distributed at intervals in the first direction and coupled to a side of the body part in a second direction. The additional part is used to form a gate of a driving transistor. The active layer includes a plurality of active structures disposed corresponding to the plurality of additional parts. Orthographic projections of the plurality of active structures on the base substrate are separated from each other.

Abstract: A Peripheral Component Interconnect express (PCIe) fault auto-repair method is provided. According to the method, when a PCIe link in a system runs, an operation state of the system is monitored by acquiring a Correctable Error (CE) error count and an Uncorrectable Error (UCE) error count in the PCIe link; when the CE error count reaches a corresponding error threshold value, or the UCE error count reaches a corresponding error threshold value, an error device is removed from the system to avoid continuous adverse influence of the error device on operation of the system. Moreover, an SI parameter register of the error device is modified according to pre-stored optimization parameters of all PCIe devices in a server, the SI parameter of the error device is automatically optimized, and the error device is re-accessed to the system after the PCIe fault repair.

Abstract: The display panel includes an active area and a border-frame area located at a periphery of the active area, the active area includes a plurality of sub-pixels and a plurality of data lines connected to the sub-pixels, and the border-frame area includes a testing area and a bonding area; the testing area includes a plurality of testing units that are arranged periodically in a first direction, each of the testing units includes one or more switching transistors, a first electrode of each of the switching transistors is connected to a testing-signal lead wire, and a second electrode is connected to one of the data lines; the bonding area includes a plurality of bonding units that are arranged periodically in the first direction, each of the bonding units includes one or more bonding pads, and each of the bonding pads is connected to one of the data lines.

Abstract: This invention provides a handrail linkage assembly for tank-type container, provided between a top side frame and a gangway plate, characterized in that: the handrail linkage assembly comprises a connecting plate welded on the top side frame, a connecting shaft is welded on the connecting plate, the connecting shaft is provided longitudinally, the top outer side of the connecting shaft is covered with a shaft sleeve, a handrail linkage is welded on the shaft sleeve, a groove is provided in the circumferential direction at the position where the connecting shaft contacts the shaft sleeve, that is, the groove is provided on the outer circumferential surface of the connecting shaft, a hole is opened on the said shaft sleeve, and a limit pin is welded inside the hole, one end of the limit pin is inserted into the groove, and the other end is located outside the shaft sleeve.

Abstract: The present disclosure provides a display panel. The display panel includes a base substrate, a first conductive layer and an active layer that are stacked in sequence. The first conductive layer includes a plurality of gate signal lines. The gate signal line includes a body part and a plurality of additional parts. An orthographic projection of the body part on the base substrate extends along a first direction. The plurality of additional parts are distributed at intervals in the first direction and coupled to a side of the body part in a second direction. The additional part is used to form a gate of a driving transistor. The active layer includes a plurality of active structures disposed corresponding to the plurality of additional parts. Orthographic projections of the plurality of active structures on the base substrate are separated from each other.

Abstract: A scan circuit is provided. The scan circuit includes a plurality of stages. A respective stage of the scan circuit includes a respective scan unit configured to provide a control signal to one or more rows of subpixels. A respective scan unit includes a first subcircuit, a second subcircuit, a third subcircuit, a fourth subcircuit. A pull-up node is coupled to the second subcircuit, the third subcircuit, and the fourth subcircuit. A pull-down node is coupled to the second subcircuit, the third subcircuit. The denoising subcircuit is coupled to a pull-up node and the input terminal, or coupled between a third power supply voltage terminal and the pull-down control node.

Abstract: The display panel includes an active area and a border-frame area located at a periphery of the active area, the active area includes a plurality of sub-pixels and a plurality of data lines connected to the sub-pixels, and the border-frame area includes a testing area and a bonding area; the testing area includes a plurality of testing units that are arranged periodically in a first direction, each of the testing units includes one or more switching transistors, a first electrode of each of the switching transistors is connected to a testing-signal lead wire, and a second electrode is connected to one of the data lines; the bonding area includes a plurality of bonding units that are arranged periodically in the first direction, each of the bonding units includes one or more bonding pads, and each of the bonding pads is connected to one of the data lines.

Abstract: Embodiments disclosed herein include multi-die packages with interconnects between the dies. In an embodiment, an electronic package comprises a package substrate, and a first die over the package substrate. In an embodiment, the first die comprises a first IO bump map, where bumps of the first IO bump map have a first pitch. In an embodiment, the electronic package further comprises a second die over the package substrate. In an embodiment, the second die comprises a second IO bump map, where bumps of the second IO bump map have a second pitch that is different than the first pitch. In an embodiment, the electronic package further comprises interconnects between the first IO bump map and the second IO bump map.

Abstract: Environmentally friendly, sustainable, and high-performance ultralight composite foams are disclosed. The composite foams are prepared from cellulose nanomaterial, polymeric material, and a crosslinking agent. The fabrication process is simple and uses only water. The composite foams exhibit an elastic strain exceeding the values reported for known nanocellulose-based foams with no reinforcement. The foams exhibit a thermal conductivity superior to that of traditional insulating materials and retain structural integrity after burning.

Abstract: A scan circuit is provided. The scan circuit includes a plurality of stages. A respective stage of the scan circuit includes a respective scan unit configured to provide a control signal to one or more rows of subpixels. A respective scan unit includes a first subcircuit, a second subcircuit, a third subcircuit, a fourth subcircuit. A pull-up node is coupled to the second subcircuit, the third subcircuit, and the fourth subcircuit. A pull-down node is coupled to the second subcircuit, the third subcircuit. The denoising subcircuit is coupled to a pull-up node and the input terminal, or coupled between a third power supply voltage terminal and the pull-down control node.

Abstract: An integrated circuit (IC) package, comprising a substrate that comprises a bridge die embedded within a dielectric. A first die comprising a first input/output (I/O) transmitter and a second die comprising a second I/O receiver and electrically coupled to the bridge die. A first signal trace and a first power conductor are within the bridge die. The first signal trace and the first power conductor are electrically coupled to the first I/O transmitter and the second I/O receiver. The first signal trace is to carry a digital signal and the first power conductor to provide a voltage for the second I/O receiver to read the digital signal.

Abstract: The present disclosure provides a driving circuit, a driving method and a display device. The driving circuit includes a first pull-down node, a first control circuit and a pull-up node reset circuit; the first control circuit is configured to control to connect the first pull-down node and the first voltage terminal under the control of the first control signal provided by the first control terminal, so that a potential of the first pull-down node is a valid voltage; the pull-up node reset circuit is configured to control to connect the pull-up node and the second voltage terminal when the potential of the first pull-down node is a valid voltage, so as to reset the potential of the pull-up node.

Abstract: A sleep-regulating tablet allowing release by stages and a preparation method thereof are provided. The tablet structurally consists of a drug-containing delayed-release tablet core, a drug-free stomach-soluble coating, a drug-free enteric coating, a drug-containing immediate-release shell, and a shell stomach-soluble coating sequentially from inside to outside. An ideal dual-stage timed drug release mode may be realized, and is especially suitable for a sleep-regulating drug, such as ramelteon.

Abstract: A Peripheral Component Interconnect express (PCIe) fault auto-repair method is provided. According to the method, when a PCIe link in a system runs, an operation state of the system is monitored by acquiring a Correctable Error (CE) error count and an Uncorrectable Error (UCE) error count in the PCIe link; when the CE error count reaches a corresponding error threshold value, or the UCE error count reaches a corresponding error threshold value, an error device is removed from the system to avoid continuous adverse influence of the error device on operation of the system. Moreover, an SI parameter register of the error device is modified according to pre-stored optimization parameters of all PCIe devices in a server, the SI parameter of the error device is automatically optimized, and the error device is re-accessed to the system after the PCIe fault repair.