Abstract: It is described a transmitter device (100) and a method for transmitting an analog signal (251, 261) via an electric cable (192).

Abstract: A primary device implementing the subject system of link establishment for single pair Ethernet may include at least one processor. The at least one processor may be configured to transmit a first synchronization sequence to a secondary device, detect a second synchronization sequence transmitted by the secondary device, the second synchronization sequence differing from the first synchronization sequence, and after detection of the second synchronization sequence, initiate a training stage, the train stage comprising exchanging training frames with the secondary device. The at least one processor may be further configured to enter a data mode for data transmissions after completion of the training stage, the data transmissions being distinct from the training frames. In the data mode, data may be forward error correction encoded and then scrambled.

Abstract: A transceiver system includes a transmitter circuit having a line driver with a programmable signal level to generate a transmit signal for transmission in an automotive environment over an unshielded-twisted pair (UTP) cable. The transceiver system further includes a physical layer (PHY) receiver. The PHY receiver includes a high-pass filter (HPF), an adaptive feed-forward equalizer (FFE) block and a noise aware adaptation block. The HPF rejects transient noise of a received signal, and the FFE block receives a digital signal and adaptively filters out narrowband continuous wave (CW) noise using an adaptation signal. The digital signal is based on the received signal, and the noise aware adaptation block receives an error signal and generates the adaptation signal. The error signal is generated based on an equalized signal of the FFE block and an estimated signal. The combined transmit and receive circuitry allow lowering emission while rejecting strong receiver automotive noises.

Abstract: A primary device implementing the subject system of link establishment for single pair Ethernet may include at least one processor. The at least one processor may be configured to transmit a first synchronization sequence to a secondary device, detect a second synchronization sequence transmitted by the secondary device, the second synchronization sequence differing from the first synchronization sequence, and after detection of the second synchronization sequence, initiate a training stage, the train stage comprising exchanging training frames with the secondary device. The at least one processor may be further configured to enter a data mode for data transmissions after completion of the training stage, the data transmissions being distinct from the training frames. In the data mode, data may be forward error correction encoded and then scrambled.

Abstract: A transceiver system includes a transmitter circuit having a line driver with a programmable signal level to generate a transmit signal for transmission in an automotive environment over an unshielded-twisted pair (UTP) cable. The transceiver system further includes a physical layer (PHY) receiver. The PHY receiver includes a high-pass filter (HPF), an adaptive feed-forward equalizer (FFE) block and a noise aware adaptation block. The HPF rejects transient noise of a received signal, and the FFE block receives a digital signal and adaptively filters out narrowband continuous wave (CW) noise using an adaptation signal. The digital signal is based on the received signal, and the noise aware adaptation block receives an error signal and generates the adaptation signal. The error signal is generated based on an equalized signal of the FFE block and an estimated signal. The combined transmit and receive circuitry allow lowering emission while rejecting strong receiver automotive noises.

Abstract: A primary device implementing the subject system of link establishment for single pair Ethernet may include at least one processor. The at least one processor may be configured to transmit a first synchronization sequence to a secondary device, detect a second synchronization sequence transmitted by the secondary device, the second synchronization sequence differing from the first synchronization sequence, and after detection of the second synchronization sequence, initiate a training stage, the train stage comprising exchanging training frames with the secondary device. The at least one processor may be further configured to enter a data mode for data transmissions after completion of the training stage, the data transmissions being distinct from the training frames. In the data mode, data may be forward error correction encoded and then scrambled.

Abstract: Systems and methods for implementing an Energy-Efficient Ethernet (EEE) communication are provided. In some aspects, a method includes identifying an EEE signal configured to be communicated via a first set of wires. The method also includes processing the EEE signal such that the processed EEE signal is configured to be communicated via a second set of wires. The second set of wires including fewer wires than the first set of wires. The method also includes communicating the processed EEE signal via the second set of wires.

Abstract: A primary device implementing the subject system of link establishment for single pair Ethernet may include at least one processor. The at least one processor may be configured to transmit a first synchronization sequence to a secondary device, detect a second synchronization sequence transmitted by the secondary device, the second synchronization sequence differing from the first synchronization sequence, and after detection of the second synchronization sequence, initiate a training stage, the train stage comprising exchanging training frames with the secondary device. The at least one processor may be further configured to enter a data mode for data transmissions after completion of the training stage, the data transmissions being distinct from the training frames. In the data mode, data may be forward error correction encoded and then scrambled.

Abstract: A primary device implementing the subject system of link establishment for single pair Ethernet may include at least one processor circuit. The at least one processor circuit may be configured to transmit a first synchronization sequence to a secondary device and to subsequently detect a second synchronization sequence, different than the first, transmitted by the secondary device. The synchronization sequences may be pseudo-noise sequences that have strong autocorrelation characteristics. The at least one processor circuit may be configured to wait a predetermined amount of time after completing the detection of the second synchronization sequence, and then may initiate a training stage. The training stage may include exchanging scrambler states of additive scramblers used by the primary and secondary devices. The at least one processor circuit may be configured to enter a data mode upon completion of training. In the data mode, data is forward error correction encoded and then scrambled.

Abstract: Systems and methods for implementing bi-directional synchronization propagation between first and second communication devices are provided. The devices are arranged in a loop-timing configuration. A method includes detecting, by the second communication device, a switching signal comprising an indication to switch a timing role of the second communication device and engaging, by the second communication device, in a synchronization handshake with the first communication device over a communication link based on the detection of the switching signal. Engaging in the synchronization handshake includes determining whether the first communication device is configured to support bi-directional synchronization propagation. The method includes switching the timing role of the second communication device based on the synchronization handshake.

Abstract: A communication technique for energy efficient Ethernet (EEE) employs a systematic block forward error correcting code (FEC). The technique aligns a low power idle (LPI) refresh signal with the FEC frame. The refresh signal includes a known reference sequence, FEC systematic symbols, and FEC parity symbols. The technique may apply shortened FEC encoding and decoding on the partial data symbols and the parity symbols.

Abstract: A primary device implementing the subject system of link establishment for single pair Ethernet may include at least one processor circuit. The at least one processor circuit may be configured to transmit a first synchronization sequence to a secondary device and to subsequently detect a second synchronization sequence, different than the first, transmitted by the secondary device. The synchronization sequences may be pseudo-noise sequences that have strong autocorrelation characteristics. The at least one processor circuit may be configured to wait a predetermined amount of time after completing the detection of the second synchronization sequence, and then may initiate a training stage. The training stage may include exchanging scrambler states of additive scramblers used by the primary and secondary devices. The at least one processor circuit may be configured to enter a data mode upon completion of training. In the data mode, data is forward error correction encoded and then scrambled.

Abstract: A communication technique for energy efficient Ethernet (EEE) employs a systematic block forward error correcting code (FEC). The technique aligns a low power idle (LPI) refresh signal with the FEC frame. The refresh signal includes a known reference sequence, FEC systematic symbols, and FEC parity symbols. The technique may apply shortened FEC encoding and decoding on the partial data symbols and the parity symbols.

Abstract: Communication devices coupled via a communication link may comprise physical layer devices that may be operable to determine presence of a received signal and to mitigate noise in the signal prior to processing and/or validating the signal. Analog and/or digital signal processing may be utilized to process the signal and/or mitigate noise in the signal. Noise mitigation may comprise near-end crosstalk cancelling and/or echo cancelling and/or may utilize local transmit signal information. Subsequent to noise mitigation, samples of the noise reduced signal may be accumulated and/or an average signal strength and/or average signal power level may be determined. The average signal strength and/or average signal power level may be compared to one or more thresholds which may be configurable and/or programmable.

Abstract: An Ethernet PHY may receive an indication from a local timing source that a local clock is suitable for propagation to a link partner. In response, a timer in the Ethernet PHY may be started. In instances that the Ethernet PHY receives, during a time period subsequent to starting the timer and before the timer reaches a predetermined value, an indication that the link partner is propagating a clock that is suitable for the Ethernet PHY to synchronize to, the Ethernet PHY may be configured as timing slave. In instances that the Ethernet PHY does not receive, during the time period subsequent to starting the timer and before the timer reaches a predetermined value, an indication that the link partner is propagating a clock that is suitable for the Ethernet PHY to synchronize to, Ethernet PHY may be configured as timing master upon the timer reaching the predetermined value.

Abstract: Communication devices coupled via a communication link may comprise physical layer devices that may be operable to determine presence of a received signal and to mitigate noise in the signal prior to processing and/or validating the signal. Analog and/or digital signal processing may be utilized to process the signal and/or mitigate noise in the signal. Noise mitigation may comprise near-end crosstalk cancelling and/or echo cancelling and/or may utilize local transmit signal information. Subsequent to noise mitigation, samples of the noise reduced signal may be accumulated and/or an average signal strength and/or average signal power level may be determined. The average signal strength and/or average signal power level may be compared to one or more thresholds which may be configurable and/or programmable.

Abstract: Communication devices coupled via a communication link may comprise physical layer devices that may be operable to determine presence of a received signal and to mitigate noise in the signal prior to processing and/or validating the signal. Analog and/or digital signal processing may be utilized to process the signal and/or mitigate noise in the signal. Noise mitigation may comprise near-end crosstalk cancelling and/or echo cancelling and/or may utilize local transmit signal information. Subsequent to noise mitigation, samples of the noise reduced signal may be accumulated and/or an average signal strength and/or average signal power level may be determined. The average signal strength and/or average signal power level may be compared to one or more thresholds which may be configurable and/or programmable.

Abstract: Aspects of a method and system for unconstrained frequency domain adaptive filtering include one or more circuits that are operable to select one or more time domain coefficients in a current filter partition. A value may be computed for each of the selected one or more time domain coefficients based on a corresponding plurality of frequency domain coefficients. The corresponding plurality of frequency domain coefficients may be adjusted based on the computed values. A subsequent plurality of frequency domain coefficients in a subsequent filter partition may be adjusted based on the computed values. Input signals may be processed in the current filter partition based on the adjusted corresponding plurality of frequency domain coefficients. A time-adjusted version of the input signals may be processed in a subsequent filter partition based on the adjusted subsequent plurality of frequency domain coefficients.

Abstract: A system for reduced pair Ethernet transmission. The system includes an interleaver that is operable to receive sets of four code symbols from a physical channel sub-layer (PCS) encoder, wherein each code symbol of each set of four code symbols is associated with one of four channels, and interleave the sets of four code symbols to generate a plurality of interleaved code symbols. The system further includes a serializer that is operable to serialize the plurality of interleaved code symbols to generate a plurality of interleaved and serialized code symbols. The system further includes a transmitter that is operable to transmit the plurality of interleaved and serialized code symbols over an Ethernet medium comprising a single twisted pair of wires.

Abstract: One or both link partners coupled via an Ethernet link may comprise a PHY device operable to initiate a wake-up interval. The PHY device may monitor parameters that may indicate Ethernet link status. Exemplary parameters may comprise a timer, communication performance metrics and/or configuration parameters. From a low power mode, the PHY device may generate a wake state idle symbol based on the monitoring and may communicate it to a local and/or a remote MAC. The local and/or remote MAC may establish a wake-up interval. The wake-up interval may comprise synchronization, circuit adaption and updating of communication parameters, which may enable control of noise cancellation functions and/or equalization functions. One or both of the link partners may transition to a low power mode after the wake-up interval and/or to an active state after the wake-up interval.