Patents by Inventor Peivand Fallah-Tehrani
Peivand Fallah-Tehrani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9424380Abstract: A system and a method are disclosed for performing static timing analysis. Information describing a distorted input waveform is received by a static timing analyzer. A transition time of the distorted input waveform is determined. Based on the determined input transition time a nominal input waveform and a corresponding nominal output waveform are received. An input waveform distortion is computed based on the nominal input waveform and the distorted input waveform. An output waveform distortion is computed based on an augmented circuit and the input waveform distortion. A distorted output waveform is computed based on the nominal output waveform and the output waveform distortion. The waveforms are represented using the distortion values which are smaller than the actual waveform values, thereby allowing for compact representation. A time-shifted version of an uncoupled input waveform is used to perform conservative timing analysis of circuits that accounts for crosstalk in the circuit.Type: GrantFiled: September 5, 2014Date of Patent: August 23, 2016Assignee: Synopsys, Inc.Inventors: Jiayong Le, Peivand Fallah Tehrani, Li Ding, Xin Wang, Ahmed Shebaita
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Publication number: 20160070834Abstract: A system and a method are disclosed for performing static timing analysis. Information describing a distorted input waveform is received by a static timing analyzer. A transition time of the distorted input waveform is determined. Based on the determined input transition time a nominal input waveform and a corresponding nominal output waveform are received. An input waveform distortion is computed based on the nominal input waveform and the distorted input waveform. An output waveform distortion is computed based on an augmented circuit and the input waveform distortion. A distorted output waveform is computed based on the nominal output waveform and the output waveform distortion. The waveforms are represented using the distortion values which are smaller than the actual waveform values, thereby allowing for compact representation. A time-shifted version of an uncoupled input waveform is used to perform conservative timing analysis of circuits that accounts for crosstalk in the circuit.Type: ApplicationFiled: September 5, 2014Publication date: March 10, 2016Inventors: Jiayong Le, Peivand Fallah Tehrani, Li Ding, Xin Wang, Ahmed Shebaita
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Patent number: 8924906Abstract: A computer-implemented method of determining an attribute of a circuit includes using a computationally expensive technique to simulate the attribute (such as timing delay or slew) of a portion of the circuit, at predetermined values of various parameters (e.g. nominal values of channel length or metal width), to obtain at least a first value of the attribute. The method also uses a computationally inexpensive technique to estimate the same attribute, thereby to obtain at least a second value which is less accurate than the first value. Then the computationally inexpensive technique is repeatedly used on other values of the parameter(s), to obtain a number of additional second values of the attribute. Applying to the additional second values, a function obtained by calibrating the at least one second value to the at least one first value, can yield calibrated estimates very quickly, which represent the attribute's variation relatively accurately.Type: GrantFiled: September 3, 2013Date of Patent: December 30, 2014Assignee: Synopsys, Inc.Inventors: Nahmsuk Oh, Peivand Fallah-Tehrani, Alireza Kasnavi, Subramanyam Sripada
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Publication number: 20140059508Abstract: A computer-implemented method of determining an attribute of a circuit includes using a computationally expensive technique to simulate the attribute (such as timing delay or slew) of a portion of the circuit, at predetermined values of various parameters (e.g. nominal values of channel length or metal width), to obtain at least a first value of the attribute. The method also uses a computationally inexpensive technique to estimate the same attribute, thereby to obtain at least a second value which is less accurate than the first value. Then the computationally inexpensive technique is repeatedly used on other values of the parameter(s), to obtain a number of additional second values of the attribute. Applying to the additional second values, a function obtained by calibrating the at least one second value to the at least one first value, can yield calibrated estimates very quickly, which represent the attribute's variation relatively accurately.Type: ApplicationFiled: September 3, 2013Publication date: February 27, 2014Applicant: Synopsys, Inc.Inventors: Nahmsuk Oh, Peivand Fallah-Tehrani, Alireza Kasnavi, Subramanyam Sripada
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Patent number: 8555235Abstract: A computer-implemented method of determining an attribute of a circuit includes using a computationally expensive technique to simulate the attribute (such as timing delay or slew) of a portion of the circuit, at predetermined values of various parameters (e.g. nominal values of channel length or metal width), to obtain at least a first value of the attribute. The method also uses a computationally inexpensive technique to estimate the same attribute, thereby to obtain at least a second value which is less accurate than the first value. Then the computationally inexpensive technique is repeatedly used on other values of the parameter(s), to obtain a number of additional second values of the attribute. Applying to the additional second values, a function obtained by calibrating the at least one second value to the at least one first value, can yield calibrated estimates very quickly, which represent the attribute's variation relatively accurately.Type: GrantFiled: January 17, 2011Date of Patent: October 8, 2013Assignee: Synopsys, Inc.Inventors: Nahmsuk Oh, Peivand Fallah-Tehrani, Alireza Kasnavl, Subramanyam Sripada
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Patent number: 8478573Abstract: A model for a circuit cell used in timing and signal integrity analysis in an integrated circuit design is automatically generated. A behavioral model, such as a gate current model is used in which the current in the circuit cell is determined as a function of the input voltage and the output voltage of the circuit cell as well as the history of at least one of the current, voltage, and charge values of the circuit cell. For example, the current in the circuit cell may be a function of the history of the current, which may be calculated incrementally using recursive convolution at each time step when using the model.Type: GrantFiled: June 23, 2005Date of Patent: July 2, 2013Assignee: Synopsys, Inc.Inventors: Li Ding, Peivand Fallah-Tehrani, Alireza Kasnavi
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Patent number: 7962876Abstract: Static timing and/or noise analysis are performed on a netlist of an integrated circuit, to estimate behavior of the netlist and to identify at least one violation by said behavior of a corresponding requirement thereon, such as setup time, hold time or bump height in a quiescent net. Thereafter, effect of engineering change order (ECO) to correct the violation are automatically analyzed, based on the layout, the parasitics, the timing and/or noise behavior, and the violation, followed by generation of a constraint on the behavior (called “ECO” constraint), such as a timing constraint and/or a noise constraint. Next, the ECO constraint is automatically used, e.g. in a place and route tool, to select an ECO repair technique, from several ECO repair techniques that can overcome the violation. The selected ECO repair technique is automatically applied to the layout, to generate a modified layout which does not have the violation.Type: GrantFiled: October 31, 2008Date of Patent: June 14, 2011Assignee: Synopsys, Inc.Inventors: Nahmsuk Oh, Peivand Fallah-Tehrani, Alireza Kasnavi
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Publication number: 20110113396Abstract: A computer-implemented method of determining an attribute of a circuit includes using a computationally expensive technique to simulate the attribute (such as timing delay or slew) of a portion of the circuit, at predetermined values of various parameters (e.g. nominal values of channel length or metal width), to obtain at least a first value of the attribute. The method also uses a computationally inexpensive technique to estimate the same attribute, thereby to obtain at least a second value which is less accurate than the first value. Then the computationally inexpensive technique is repeatedly used on other values of the parameter(s), to obtain a number of additional second values of the attribute. Applying to the additional second values, a function obtained by calibrating the at least one second value to the at least one first value, can yield calibrated estimates very quickly, which represent the attribute's variation relatively accurately.Type: ApplicationFiled: January 17, 2011Publication date: May 12, 2011Inventors: Nahmsuk Oh, Peivand Fallah-Tehrani, Alireza Kasnavi, Subramanyam Sripada
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Patent number: 7900165Abstract: A computer-implemented method of determining an attribute of a circuit includes using a computationally expensive technique to simulate the attribute (such as timing delay or slew) of a portion of the circuit, at predetermined values of various parameters (e.g. nominal values of channel length or metal width), to obtain at least a first value of the attribute. The method also uses a computationally inexpensive technique to estimate the same attribute, thereby to obtain at least a second value which is less accurate than the first value. Then the computationally inexpensive technique is repeatedly used on other values of the parameter(s), to obtain a number of additional second values of the attribute. Applying to the additional second values, a function obtained by calibrating the at least one second value to the at least one first value, can yield calibrated estimates very quickly, which represent the attribute's variation relatively accurately.Type: GrantFiled: March 30, 2007Date of Patent: March 1, 2011Assignee: Synopsys, Inc.Inventors: Nahmsuk Oh, Peivand Fallah-Tehrani, Alireza Kasnavi, Subramanyam Sripada
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Publication number: 20090055787Abstract: Static timing and/or noise analysis are performed on a netlist of an integrated circuit, to estimate behavior of the netlist and to identify at least one violation by said behavior of a corresponding requirement thereon, such as setup time, hold time or bump height in a quiescent net. Thereafter, effect of engineering change order (ECO) to correct the violation are automatically analyzed, based on the layout, the parasitics, the timing and/or noise behavior, and the violation, followed by generation of a constraint on the behavior (called “ECO” constraint), such as a timing constraint and/or a noise constraint. Next, the ECO constraint is automatically used, e.g. in a place and route tool, to select an ECO repair technique, from several ECO repair techniques that can overcome the violation. The selected ECO repair technique is automatically applied to the layout, to generate a modified layout which does not have the violation.Type: ApplicationFiled: October 31, 2008Publication date: February 26, 2009Inventors: Nahmsuk Oh, Peivand Fallah-Tehrani, Alireza Kasnavi
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Patent number: 7454731Abstract: Static timing and/or noise analysis are performed on a netlist of an integrated circuit, to estimate behavior of the netlist and to identify at least one violation by said behavior of a corresponding requirement thereon, such as setup time, hold time or bump height in a quiescent net. Thereafter, effect of engineering change order (ECO) to correct the violation are automatically analyzed, based on the layout, the parasitics, the timing and/or noise behavior, and the violation, followed by generation of a constraint on the behavior (called “ECO” constraint), such as a timing constraint and/or a noise constraint. Next, the ECO constraint is automatically used, e.g. in a place and route tool, to select an ECO repair technique, from several ECO repair techniques that can overcome the violation. The selected ECO repair technique is automatically applied to the layout, to generate a modified layout which does not have the violation.Type: GrantFiled: September 22, 2006Date of Patent: November 18, 2008Assignee: Synopsys, Inc.Inventors: Nahmsuk Oh, Peivand Fallah-Tehrani, Alireza Kasnavi
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Publication number: 20080243414Abstract: A computer-implemented method of determining an attribute of a circuit includes using a computationally expensive technique to simulate the attribute (such as timing delay or slew) of a portion of the circuit, at predetermined values of various parameters (e.g. nominal values of channel length or metal width), to obtain at least a first value of the attribute. The method also uses a computationally inexpensive technique to estimate the same attribute, thereby to obtain at least a second value which is less accurate than the first value. Then the computationally inexpensive technique is repeatedly used on other values of the parameter(s), to obtain a number of additional second values of the attribute. Applying to the additional second values, a function obtained by calibrating the at least one second value to the at least one first value, can yield calibrated estimates very quickly, which represent the attribute's variation relatively accurately.Type: ApplicationFiled: March 30, 2007Publication date: October 2, 2008Applicant: Synopsys, Inc.Inventors: Nahmsuk Oh, Peivand Fallah-Tehrani, Alireza Kasnavi, Subramanyam Sripada
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Patent number: 7272807Abstract: An equivalent waveform for a distorted waveform used in timing and signal integrity analysis in the design of an integrated circuit is automatically generated. The equivalent waveform is produced by calculating the transition quantity of a first non-distorted waveform. The transition quantity is the amount of transition of the first non-distorted waveform that is required for the cell to produce an output waveform with a predetermined end voltage. The end point of the transition period for the distorted waveform is then determined based on when the distorted waveform has accumulated the same transition quantity. The equivalent waveform can then be formed by computing a second non-distorted waveform such that the end point of the transition period for the second non-distorted waveform coincides with the end point of the transition period for the distorted waveform.Type: GrantFiled: March 2, 2005Date of Patent: September 18, 2007Assignee: Synopsys, Inc.Inventors: Li Ding, Peivand Fallah Tehrani, Alireza Kasnavi
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Patent number: 7263676Abstract: One embodiment of the invention provides a system that analyzes the propagation of noise through an integrated circuit. During operation, the system obtains an input noise signal to be applied to a cell within the integrated circuit. The system then looks up parameters specifying how noise affects the cell, and then uses the parameters to determine how the input noise signal affects the cell. This can involve determining if the input noise signal will cause the cell to fail and/or determining a propagated noise signal that emanates from the cell.Type: GrantFiled: April 9, 2003Date of Patent: August 28, 2007Assignee: Synopsys, Inc.Inventors: Alexander Gyure, Jindrich Zejda, Peivand Fallah-Tehrani, Wenyuan Wang, Chi-Chong Lo, Seyed Alireza Kasnavi, Mahmoud Shahram, Yansheng Luo, William Chiu-Ting Shu
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Publication number: 20070010981Abstract: A model for a circuit cell used in timing and signal integrity analysis in an integrated circuit design is automatically generated. A behavioral model, such as a gate current model is used in which the current in the circuit cell is determined as a function of the input voltage and the output voltage of the circuit cell as well as the history of at least one of the current, voltage, and charge values of the circuit cell. For example, the current in the circuit cell may be a function of the history of the current, which may be calculated incrementally using recursive convolution at each time step when using the model.Type: ApplicationFiled: June 23, 2005Publication date: January 11, 2007Applicant: Synopsys, Inc.Inventors: Li Ding, Peivand Fallah-Tehrani, Alireza Kasnavi
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Publication number: 20060200784Abstract: An equivalent waveform for a distorted waveform used in timing and signal integrity analysis in the design of an integrated circuit is automatically generated. The equivalent waveform is produced by calculating the transition quantity of a first non-distorted waveform. The transition quantity is the amount of transition of the first non-distorted waveform that is required for the cell to produce an output waveform with a predetermined end voltage. The end point of the transition period for the distorted waveform is then determined based on when the distorted waveform has accumulated the same transition quantity. The equivalent waveform can then be formed by computing a second non-distorted waveform such that the end point of the transition period for the second non-distorted waveform coincides with the end point of the transition period for the distorted waveform.Type: ApplicationFiled: March 2, 2005Publication date: September 7, 2006Applicant: Synopsys, Inc.Inventors: Li Ding, Peivand Fallah-Tehrani, Alireza Kasnavi
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Patent number: 7007252Abstract: One embodiment of the invention provides a system that characterizes cells within an integrated circuit. During operation, the system obtains a number of input noise signals to be applied to the cell. The system then simulates responses of the cell to each of the input noise signals, and stores a representation of the responses. This allows a subsequent analysis operation to access the stored representation to determine a response of the cell instead of having to perform a time-consuming simulation operation.Type: GrantFiled: April 9, 2003Date of Patent: February 28, 2006Assignee: Synopsys, Inc.Inventors: Alexander Gyure, Jindrich Zejda, Peivand Fallah-Tehrani, Wenyuan Wang, Chi-Chong Lo, Mahmoud Shahram, Yansheng Luo, William Chiu-Ting Shu, Seyed Alireza Kasnavi
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Publication number: 20040205682Abstract: One embodiment of the invention provides a system that analyzes the propagation of noise through an integrated circuit. During operation, the system obtains an input noise signal to be applied to a cell within the integrated circuit. The system then looks up parameters specifying how noise affects the cell, and then uses the parameters to determine how the input noise signal affects the cell. This can involve determining if the input noise signal will cause the cell to fail and/or determining a propagated noise signal that emanates from the cell.Type: ApplicationFiled: April 9, 2003Publication date: October 14, 2004Inventors: Alexander Gyure, Jindrich Zejda, Peivand Fallah-Tehrani, Wenyuan Wang, Chi-Chong Lo, Seyed Alireza Kasnavi, Mahmoud Shahram, Yansheng Luo, William Chiu-Ting Shu
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Publication number: 20040205680Abstract: One embodiment of the invention provides a system that characterizes cells within an integrated circuit. During operation, the system obtains a number of input noise signals to be applied to the cell. The system then simulates responses of the cell to each of the input noise signals, and stores a representation of the responses. This allows a subsequent analysis operation to access the stored representation to determine a response of the cell instead of having to perform a time-consuming simulation operation.Type: ApplicationFiled: April 9, 2003Publication date: October 14, 2004Applicant: Entire InterestInventors: Alexander Gyure, Jindrich Zejda, Peivand Fallah-Tehrani, Wenyuan Wang, Chi-Chong Lo, Mahmoud Shahram, Yansheng Luo, William Chiu-Ting Shu, SEYED ALIREZA KASNAVI
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Patent number: 6405348Abstract: A method for static timing analysis of deep sub-micron devices in presence of crosstalk. The present invention provides an efficient platform for fast and accurate static timing verification of large scale transistor and cell level netlists, with coupled interconnects and high switching speeds. The present invention also provides a novel approach to solve the coupled noise problem in static timing verification. The present invention also provides for a method of determining worst case aggressor switching time for a cross-coupled interconnect stage. After the worst case aggressor switching time is determined, the netlist is then resimulated using the worst case aggressor switching time to determine more accuate stage delay and slew of the interconnect stage. The output waveform is recorded and utilized as the input of subsequent stages.Type: GrantFiled: January 11, 2000Date of Patent: June 11, 2002Assignee: Synopsys, Inc.Inventors: Peivand Fallah-Tehrani, Shang-Woo Chyou