Patents by Inventor Peixuan Tan

Peixuan Tan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10937481
    Abstract: Various implementations described herein are directed to a device having memory circuitry having bitcells coupled together via bitlines. The device may include polarity swapping circuitry having multiple conductive paths that are configured to couple the bitlines together. In some instances, first paths of the multiple conductive paths couple the bitlines together via first passgates, and second paths of the multiple conductive paths couple the bitlines together via second passgates.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: March 2, 2021
    Assignee: Arm Limited
    Inventors: Andy Wangkun Chen, Peixuan Tan
  • Publication number: 20210043241
    Abstract: Various implementations described herein are directed to a device having memory circuitry having bitcells coupled together via bitlines. The device may include polarity swapping circuitry having multiple conductive paths that are configured to couple the bitlines together. In some instances, first paths of the multiple conductive paths couple the bitlines together via first passgates, and second paths of the multiple conductive paths couple the bitlines together via second passgates.
    Type: Application
    Filed: August 7, 2019
    Publication date: February 11, 2021
    Inventors: Andy Wangkun Chen, Peixuan Tan
  • Patent number: 10741227
    Abstract: Various implementations described herein refer to an integrated circuit having a first pulse generator and a second pulse generator. The first pulse generator generates a first clock pulse for a two pulse sequence based on one or more input signals. The second pulse generator is coupled to the first pulse generator and generates a second clock pulse for the two pulse sequence based on the one or more input signals. The second pulse generator has a single stack clock driver that provides an output clock signal having the two pulse sequence.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: August 11, 2020
    Assignee: Arm Limited
    Inventors: Kumaraswamy Ramanathan, Peixuan Tan, Andy Wangkun Chen
  • Publication number: 20200051602
    Abstract: Various implementations described herein refer to an integrated circuit having a first pulse generator and a second pulse generator. The first pulse generator generates a first clock pulse for a two pulse sequence based on one or more input signals. The second pulse generator is coupled to the first pulse generator and generates a second clock pulse for the two pulse sequence based on the one or more input signals. The second pulse generator has a single stack clock driver that provides an output clock signal having the two pulse sequence.
    Type: Application
    Filed: August 8, 2018
    Publication date: February 13, 2020
    Inventors: Kumaraswamy Ramanathan, Peixuan Tan, Andy Wangkun Chen