Patents by Inventor Peizhen Hong
Peizhen Hong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240107757Abstract: Embodiments of semiconductor devices and methods for forming the semiconductor devices are disclosed. In an example, a method for forming device openings includes forming a material layer over a first region and a second region of a substrate, the first region being adjacent to the second region, forming a mask layer over the material layer, the mask layer covering the first region and the second region, and forming a patterning layer over the mask layer. The patterning layer covers the first region and the second region and including openings corresponding to the first region. The plurality of openings includes a first opening adjacent to a boundary between the first region and the second region and a second opening further away from the boundary. Along a plane parallel to a top surface of the substrate, a size of the first opening is greater than a size of the second opening.Type: ApplicationFiled: December 8, 2023Publication date: March 28, 2024Inventors: Jia He, Haihui Huang, Fandong Liu, Yaohua Yang, Peizhen Hong, Zhiliang Xia, Zongliang Huo, Yaobin Feng, Baoyou Chen, Qingchen Cao
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Patent number: 11903195Abstract: Embodiments of semiconductor devices and methods for forming the semiconductor devices are disclosed. In an example, a method for forming device openings includes forming a material layer over a first region and a second region of a substrate, the first region being adjacent to the second region, forming a mask layer over the material layer, the mask layer covering the first region and the second region, and forming a patterning layer over the mask layer. The patterning layer covers the first region and the second region and including openings corresponding to the first region. The plurality of openings includes a first opening adjacent to a boundary between the first region and the second region and a second opening further away from the boundary. Along a plane parallel to a top surface of the substrate, a size of the first opening is greater than a size of the second opening.Type: GrantFiled: January 19, 2023Date of Patent: February 13, 2024Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Jia He, Haihui Huang, Fandong Liu, Yaohua Yang, Peizhen Hong, Zhiliang Xia, Zongliang Huo, Yaobin Feng, Baoyou Chen, Qingchen Cao
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Publication number: 20230413560Abstract: A memory device includes a substrate, a stack over the substrate, and a gate line slit extending along a first direction and dividing the stack into two portions. The stack includes a connection portion that connects the two portions of the stack. The connection portion includes at least two sub-connection portions along a second direction perpendicular to the first direction. The gate line slit includes at least two portions along the first direction. Each sub-connection portion is between adjacent two portions of the gate line slit.Type: ApplicationFiled: August 22, 2023Publication date: December 21, 2023Inventors: Qiang Xu, Fandong Liu, Zongliang Huo, Zhiliang Xia, Yaohua Yang, Peizhen Hong, Wenyu Hua, Jia He
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Patent number: 11792989Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device comprises a substrate, a stack structure on the substrate, and at least one gate line slit extending along a first direction substantially parallel to a top surface of the substrate, and dividing the stack structure into at least two portions. The stack structure includes at least one connection portion that divides the at least one gate line slit, and conductively connects the at least two portions.Type: GrantFiled: October 25, 2021Date of Patent: October 17, 2023Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Qiang Xu, Fandong Liu, Zongliang Huo, Zhiliang Xia, Yaohua Yang, Peizhen Hong, Wenyu Hua, Jia He
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Publication number: 20230157020Abstract: Embodiments of semiconductor devices and methods for forming the semiconductor devices are disclosed. In an example, a method for forming device openings includes forming a material layer over a first region and a second region of a substrate, the first region being adjacent to the second region, forming a mask layer over the material layer, the mask layer covering the first region and the second region, and forming a patterning layer over the mask layer. The patterning layer covers the first region and the second region and including openings corresponding to the first region. The plurality of openings includes a first opening adjacent to a boundary between the first region and the second region and a second opening further away from the boundary. Along a plane parallel to a top surface of the substrate, a size of the first opening is greater than a size of the second opening.Type: ApplicationFiled: January 19, 2023Publication date: May 18, 2023Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Jia HE, Haihui HUANG, Fandong LIU, Yaohua YANG, Peizhen HONG, Zhiliang XIA, Zongliang HUO, Yaobin FENG, Baoyou CHEN, Qingchen CAO
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Patent number: 11574919Abstract: Embodiments of semiconductor devices and methods for forming the semiconductor devices are disclosed. In an example, a method for forming device openings includes forming a material layer over a first region and a second region of a substrate, the first region being adjacent to the second region, forming a mask layer over the material layer, the mask layer covering the first region and the second region, and forming a patterning layer over the mask layer. The patterning layer covers the first region and the second region and including openings corresponding to the first region. The plurality of openings includes a first opening adjacent to a boundary between the first region and the second region and a second opening further away from the boundary. Along a plane parallel to a top surface of the substrate, a size of the first opening is greater than a size of the second opening.Type: GrantFiled: September 10, 2020Date of Patent: February 7, 2023Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Jia He, Haihui Huang, Fandong Liu, Yaohua Yang, Peizhen Hong, Zhiliang Xia, Zongliang Huo, Yaobin Feng, Baoyou Chen, Qingchen Cao
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Publication number: 20220059564Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device comprises a substrate, a stack structure on the substrate, and at least one gate line slit extending along a first direction substantially parallel to a top surface of the substrate, and dividing the stack structure into at least two portions. The stack structure includes at least one connection portion that divides the at least one gate line slit, and conductively connects the at least two portions.Type: ApplicationFiled: October 25, 2021Publication date: February 24, 2022Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Qiang XU, Fandong LIU, Zongliang HUO, Zhiliang XIA, Yaohua YANG, Peizhen HONG, Wenyu HUA, Jia HE
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Patent number: 11222903Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the method comprises: providing a substrate; forming an alternating stack over the substrate, the alternating stack comprising a plurality of tiers of sacrificial layer/insulating layer pairs extending along a first direction substantially parallel to a top surface of the substrate; forming a plurality of tiers of word lines extending along the first direction based on the alternating stack; forming at least one connection portion conductively connecting two or more of the word lines of the plurality of tiers of word lines; and forming at least one metal contact via conductively shared by connected word lines, the at least one metal contact via being connected to at least one metal interconnect.Type: GrantFiled: April 8, 2020Date of Patent: January 11, 2022Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Qiang Xu, Fandong Liu, Zongliang Huo, Zhiliang Xia, Yaohua Yang, Peizhen Hong, Wenyu Hua, Jia He
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Publication number: 20210151458Abstract: Embodiments of semiconductor devices and methods for forming the semiconductor devices are disclosed. In an example, a method for forming device openings includes forming a material layer over a first region and a second region of a substrate, the first region being adjacent to the second region, forming a mask layer over the material layer, the mask layer covering the first region and the second region, and forming a patterning layer over the mask layer. The patterning layer covers the first region and the second region and including openings corresponding to the first region. The plurality of openings includes a first opening adjacent to a boundary between the first region and the second region and a second opening further away from the boundary. Along a plane parallel to a top surface of the substrate, a size of the first opening is greater than a size of the second opening.Type: ApplicationFiled: September 10, 2020Publication date: May 20, 2021Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Jia HE, Haihui HUANG, Fandong LIU, Yaohua YANG, Peizhen HONG, Zhiliang XIA, Zongliang HUO, Yaobin FENG, Baoyou CHEN, Qingchen CAO
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Patent number: 10804283Abstract: Embodiments of semiconductor devices and methods for forming the semiconductor devices are disclosed. In an example, a method for forming device openings includes forming a material layer over a first region and a second region of a substrate, the first region being adjacent to the second region, forming a mask layer over the material layer, the mask layer covering the first region and the second region, and forming a patterning layer over the mask layer. The patterning layer covers the first region and the second region and including openings corresponding to the first region. The plurality of openings includes a first opening adjacent to a boundary between the first region and the second region and a second opening further away from the boundary. Along a plane parallel to a top surface of the substrate, a size of the first opening is greater than a size of the second opening.Type: GrantFiled: July 26, 2018Date of Patent: October 13, 2020Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Jia He, Haihui Huang, Fandong Liu, Yaohua Yang, Peizhen Hong, Zhiliang Xia, Zongliang Huo, Yaobin Feng, Baoyou Chen, Qingchen Cao
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Publication number: 20200243557Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the method comprises: providing a substrate; forming an alternating stack over the substrate, the alternating stack comprising a plurality of tiers of sacrificial layer/insulating layer pairs extending along a first direction substantially parallel to a top surface of the substrate; forming a plurality of tiers of word lines extending along the first direction based on the alternating stack; forming at least one connection portion conductively connecting two or more of the word lines of the plurality of tiers of word lines; and forming at least one metal contact via conductively shared by connected word lines, the at least one metal contact via being connected to at least one metal interconnect.Type: ApplicationFiled: April 8, 2020Publication date: July 30, 2020Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Qiang XU, Fandong LIU, Zongliang HUO, Zhiliang XIA, Yaohua YANG, Peizhen HONG, Wenyu HUA, Jia HE
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Patent number: 10651192Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a substrate, a first tier of conductor layers of a first length comprising a first plurality of conductor layers extending along a first direction over the substrate. The first direction is substantially parallel to a top surface of the substrate. In some embodiments, the memory device also includes at least one connection portion conductively connecting two or more conductor layers of the first tier, and a first metal contact via conductively shared by connected conductor layers of the first tier and connected to a first metal interconnect.Type: GrantFiled: July 26, 2018Date of Patent: May 12, 2020Assignee: Yangtze Memory Technologies Co, Ltd.Inventors: Qiang Xu, Fandong Liu, Zongliang Huo, Zhiliang Xia, Yaohua Yang, Peizhen Hong, Wenyu Hua, Jia He
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Publication number: 20190043883Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a substrate, a first tier of conductor layers of a first length comprising a first plurality of conductor layers extending along a first direction over the substrate. The first direction is substantially parallel to a top surface of the substrate. In some embodiments, the memory device also includes at least one connection portion conductively connecting two or more conductor layers of the first tier, and a first metal contact via conductively shared by connected conductor layers of the first tier and connected to a first metal interconnect.Type: ApplicationFiled: July 26, 2018Publication date: February 7, 2019Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Qiang XU, Fandong LIU, Zongliang HUO, Zhiliang XIA, Yaohua YANG, Peizhen HONG, Wenyu HUA, Jia HE
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Publication number: 20190013327Abstract: Embodiments of semiconductor devices and methods for forming the semiconductor devices are disclosed. In an example, a method for forming device openings includes forming a material layer over a first region and a second region of a substrate, the first region being adjacent to the second region, forming a mask layer over the material layer, the mask layer covering the first region and the second region, and forming a patterning layer over the mask layer. The patterning layer covers the first region and the second region and including openings corresponding to the first region. The plurality of openings includes a first opening adjacent to a boundary between the first region and the second region and a second opening further away from the boundary. Along a plane parallel to a top surface of the substrate, a size of the first opening is greater than a size of the second opening.Type: ApplicationFiled: July 26, 2018Publication date: January 10, 2019Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Jia He, Haihui Huang, Fandong Liu, Yaohua Yang, Peizhen Hong, Zhiliang Xia, Zongliang Huo, Yaobin Feng, Baoyou Chen, Qingchen Cao
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Publication number: 20190013326Abstract: The present disclosure describes methods and structures for three-dimensional memory devices. The methods include providing a bottom substrate and forming a plurality of doped layers over the bottom substrate. The plurality of doped layers has a total thickness in a thickness range such that a top surface of the plurality of doped layers is substantially flat and a doping concentration of each of the plurality of doped layers is substantially uniform along a direction substantially perpendicular to the top surface of the plurality of doped layers.Type: ApplicationFiled: July 26, 2018Publication date: January 10, 2019Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Wenyu HUA, Zhiliang XIA, Yangbo JIANG, Fandong LIU, Peizhen HONG, Fenghua FU, Yaohua YANG, Ming ZENG, Zongliang HUO
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Patent number: 9006057Abstract: A method of manufacturing a semiconductor device is disclosed. In one embodiment, the method comprises: forming a gate stack on a substrate; etching the substrate on both sides of the gate stack to form C-shaped source/drain grooves; and wet-etching the C-shaped source/drain grooves to form ?-shaped source/drain grooves. With this method, it is possible to effectively increase stress applied to a channel region, to accurately control a depth of the source/drain grooves, and to reduce roughness of side walls and bottom portions of the grooves and thus reduce defects by etching the C-shaped source/drain grooves and then further wet-etching them to form the ?-shaped source/drain grooves.Type: GrantFiled: July 31, 2012Date of Patent: April 14, 2015Assignee: Institute of Microelectronics, Chinese Academy of SciencesInventors: Changliang Qin, Peizhen Hong, Huaxiang Yin
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Publication number: 20140057404Abstract: A method of manufacturing a semiconductor device is disclosed. In one embodiment, the method comprises: forming a gate stack on a substrate; etching the substrate on both sides of the gate stack to form C-shaped source/drain grooves; and wet-etching the C-shaped source/drain grooves to form ?-shaped source/drain grooves. With this method, it is possible to effectively increase stress applied to a channel region, to accurately control a depth of the source/drain grooves, and to reduce roughness of side walls and bottom portions of the grooves and thus reduce defects by etching the C-shaped source/drain grooves and then further wet-etching them to form the ?-shaped source/drain grooves.Type: ApplicationFiled: July 31, 2012Publication date: February 27, 2014Applicant: Institute of Microelectronics, Chinese Academy of SciencesInventors: Changliang Qin, Peizhen Hong, Huaxiang Yin