Patents by Inventor Pekka Ojala
Pekka Ojala has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10418989Abstract: In order to get the best of both high and low common mode ranges, an adaptive body biasing method using a pair of replica devices is implemented. Each replica device corresponds to a NMOS (or PMOS) device that constitutes the input pair used in a logic circuit or other type of integrated circuits. This configuration helps to increase the threshold voltage of the device, utilizing body effect, at high input common mode voltage, as desired for NMOS, and at low input common mode voltage, as desired for PMOS. At the same time, this configuration scales the threshold back to normal at low input common mode voltages, thereby countering the negative impact of body effect. In short, the body bias applied to the NMOS (or PMOS) device helps in adapting the threshold voltage to the operating condition.Type: GrantFiled: October 15, 2018Date of Patent: September 17, 2019Assignee: Exar CorporationInventors: Vinit Jayaraj, Pekka Ojala, John Tabler
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Publication number: 20190052261Abstract: In order to get the best of both high and low common mode ranges, an adaptive body biasing method using a pair of replica devices is implemented. Each replica device corresponds to a NMOS (or PMOS) device that constitutes the input pair used in a logic circuit or other type of integrated circuits. This configuration helps to increase the threshold voltage of the device, utilizing body effect, at high input common mode voltage, as desired for NMOS, and at low input common mode voltage, as desired for PMOS. At the same time, this configuration scales the threshold back to normal at low input common mode voltages, thereby countering the negative impact of body effect. In short, the body bias applied to the NMOS (or PMOS) device helps in adapting the threshold voltage to the operating condition.Type: ApplicationFiled: October 15, 2018Publication date: February 14, 2019Inventors: Vinit JAYARAJ, Pekka OJALA, John TABLER
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Patent number: 10103728Abstract: In order to get the best of both high and low common mode ranges, an adaptive body biasing method using a pair of replica devices is implemented. Each replica device corresponds to a NMOS (or PMOS) device that constitutes the input pair used in a logic circuit or other type of integrated circuits. This configuration helps to increase the threshold voltage of the device, utilizing body effect, at high input common mode voltage, as desired for NMOS, and at low input common mode voltage, as desired for PMOS. At the same time, this configuration scales the threshold back to normal at low input common mode voltages, thereby countering the negative impact of body effect. In short, the body bias applied to the NMOS (or PMOS) device helps in adapting the threshold voltage to the operating condition.Type: GrantFiled: March 30, 2017Date of Patent: October 16, 2018Assignee: Exar CorporationInventors: Vinit Jayaraj, Pekka Ojala, John Tabler
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Publication number: 20180287604Abstract: In order to get the best of both high and low common mode ranges, an adaptive body biasing method using a pair of replica devices is implemented. Each replica device corresponds to a NMOS (or PMOS) device that constitutes the input pair used in a logic circuit or other type of integrated circuits. This configuration helps to increase the threshold voltage of the device, utilizing body effect, at high input common mode voltage, as desired for NMOS, and at low input common mode voltage, as desired for PMOS. At the same time, this configuration scales the threshold back to normal at low input common mode voltages, thereby countering the negative impact of body effect. In short, the body bias applied to the NMOS (or PMOS) device helps in adapting the threshold voltage to the operating condition.Type: ApplicationFiled: March 30, 2017Publication date: October 4, 2018Inventors: Vinit JAYARAJ, Pekka OJALA, John TABLER
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Patent number: 7057241Abstract: A double well structure beneath an inductor to isolate it from the substrate. Contacts are provided for the deeper well and the substrate, to reverse bias the junction between the substrate and the deep well. In one embodiment, for a P-substrate, the deep well is an N-well, and the other well is a P-well. Both the N-well junction with the substrate, and the junction between the N-well and the P-well are reverse biased. This improves the quality factor of the inductor structure above the wells by reducing eddy currents. In one embodiment, the P-well is striped. The deeper N-well extends upward into the gaps between the stripes. The stripes will further reduce the amount of eddy current by adding a reverse biased sidewall junction to the eddy current path, further helping to increase the quality factor of the inductor.Type: GrantFiled: December 20, 2002Date of Patent: June 6, 2006Assignee: Exar CorporationInventor: Pekka Ojala
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Publication number: 20060065947Abstract: A double well structure beneath an inductor to isolate it from the substrate. Contacts are provided for the deeper well and the substrate, to reverse bias the junction between the substrate and the deep well. In one embodiment, for a P-substrate, the deep well is an N-well, and the other well is a P-well. Both the N-well junction with the substrate, and the junction between the N-well and the P-well are reverse biased. This improves the quality factor of the inductor structure above the wells by reducing eddy currents. In one embodiment, the P-well is striped. The deeper N-well extends upward into the gaps between the stripes. The stripes will further reduce the amount of eddy current by adding a reverse biased sidewall junction to the eddy current path, further helping to increase the quality factor of the inductor.Type: ApplicationFiled: December 20, 2002Publication date: March 30, 2006Applicant: Exar CorporationInventor: Pekka Ojala
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Publication number: 20040085700Abstract: A method and apparatus for implementing trimming circuits. More particularly, embodiments of the present invention provide a transistor that supplies sufficient current to trim a trimming fuse when the transistor is powered up and after it receives a select signal at its gate. When the trimming fuse is trimmed, it decouples undesired electrical connections in a circuit. Also provided is a delay structure that adds an RC delay to the select signal. The RC delay is of a sufficiently long duration so as to decrease the switching speed of the transistor. The delay structure also provides a pass filter to filter power and voltage spikes in the select signal.Type: ApplicationFiled: October 28, 2003Publication date: May 6, 2004Applicant: Exar CorporationInventors: Andras Szabo, Pekka Ojala
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Patent number: 6693783Abstract: A method and apparatus for implementing trimming circuits. More particularly, embodiments of the present invention provide a transistor that supplies sufficient current to trim a trimming fuse when the transistor is powered up and after it receives a select signal at its gate. When the trimming fuse is trimmed, it decouples undesired electrical connections in a circuit. Also provided is a delay structure that adds an RC delay to the select signal. The RC delay is of a sufficiently long duration so as to decrease the switching speed of the transistor. The delay structure also provides a pass filter to filter power and voltage spikes in the select signal.Type: GrantFiled: April 8, 2002Date of Patent: February 17, 2004Assignee: Exar CorporationInventors: Andras Szabo, Pekka Ojala
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Publication number: 20030197996Abstract: A method and apparatus for implementing trimming circuits. More particularly, embodiments of the present invention provide a transistor that supplies sufficient current to trim a trimming fuse when the transistor is powered up and after it receives a select signal at its gate. When the trimming fuse is trimmed, it decouples undesired electrical connections in a circuit. Also provided is a delay structure that adds an RC delay to the select signal. The RC delay is of a sufficiently long duration so as to decrease the switching speed of the transistor. The delay structure also provides a pass filter to filter power and voltage spikes in the select signal.Type: ApplicationFiled: April 8, 2002Publication date: October 23, 2003Applicant: Exar CorporationInventors: Andras Szabo, Pekka Ojala
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Patent number: 6597222Abstract: A circuit for putting an output driver into a high impedance state upon failure of the power supply. This is accomplished by providing a first transistor that is connected between the power supply and the n-well to charge the n-well node of the PMOS drive transistor. Upon failure of the supply voltage, a number of transistors are connected to couple the n-well and a gate of the PMOS drive transistor to the output line, so that they track the voltage level of the output, thereby preventing forward biasing of the P+/n-well diode.Type: GrantFiled: October 15, 2001Date of Patent: July 22, 2003Assignee: Exar CorporationInventors: Loi Thanh Le, Pekka Ojala, Bahram Fotouhi
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Publication number: 20030071660Abstract: A circuit for putting an output driver into a high impedance state upon failure of the power supply. This is accomplished by providing a first transistor that is connected between the power supply and the n-well to charge the n-well node of the PMOS drive transistor. Upon failure of the supply voltage, a number of transistors are connected to couple the n-well and a gate of the PMOS drive transistor to the output line, so that they track the voltage level of the output, thereby preventing forward biasing of the P+/n-well diode.Type: ApplicationFiled: October 15, 2001Publication date: April 17, 2003Applicant: Exar CorporationInventors: Loi Thanh Le, Pekka Ojala, Bahram Fotouhi