Abstract: PNP high power transistors are made in high yield by a process wherein the base diffusion step is conducted in a diffusion furnace wherein phosphorus is deposited on the walls of the furnace. This results in a sharp collector to base junction.

Abstract: An improved process for forming electrically-isolated regions in integrated circuits in the form of dielectric moats surrounding the regions and P-N junctions underlying the regions. Moats or notches are etched into the substrate prior to the formation of the buried isolation layer or further device information. A dielectric material such as silicon dioxide is deposited in the notches or moats and polycrystalline silicon is thereafter grown on the surface of the wafer to fill the notches or moats. The excess polysilicon formed on the surface of the wafer is then removed by mechanical lapping or polishing. Since there has been no doping or epitaxial growth, the wafer may be lapped directly to the substrate to remove all of the polysilicon and oxide from the surface while leaving the notches or moats lined with dielectric material and filled with polysilicon. There is thus no criticality to the lapping operation.