Abstract: A feed-forward equalizer includes a shift register, a look-up table circuit, a selection circuit and an output terminal. The shift register temporarily stores and shifts input data based on a clock signal to obtain multiple shifted input data. The look-up table circuit has multiple processed signals. The processed signals are obtained by logical operation of multiple coefficients. An input terminal of the selection circuit is coupled to the look-up table circuit. A control terminal of the selection circuit receives the shifted input data. The selection circuit selects at least one of the processed signals of the look-up table circuit as a selected signal based on the shifted input data. The output terminal provides an output signal according to the selected signal.

Abstract: A feed-forward equalizer includes a shift register, a look-up table circuit, a selection circuit and an output terminal. The shift register temporarily stores and shifts input data based on a clock signal to obtain multiple shifted input data. The look-up table circuit has multiple processed signals. The processed signals are obtained by logical operation of multiple coefficients. An input terminal of the selection circuit is coupled to the look-up table circuit. A control terminal of the selection circuit receives the shifted input data. The selection circuit selects at least one of the processed signals of the look-up table circuit as a selected signal based on the shifted input data. The output terminal provides an output signal according to the selected signal.

Abstract: A receiver includes a channel compensator, a decoder and an adaptive controller. The channel compensator performs channel compensation on an input data signal to generates a feed-in data signal. The decoder demultiplexes a to-be-decoded data signal that originates from the feed-in data signal into multiple demultiplexed data signals, and decoding the demultiplexed data signals respectively into multiple decoded signals. Based on a decoded output that originates from the decoded signals, the adaptive controller performs adaptive calibration on the channel compensator to adjust a gain of the channel compensator with reference to an error portion of a first sample of the decoded signals and a data portion of a second sample of the decoded signals that is generated before the generation of the first sample of the decoded signals.

Abstract: A decoder includes a demultiplexer and a number (P) of ADCs, where P?2. The demultiplexer receives a to-be-decoded data signal that is in a PAM-2M format, and demultiplexes the to-be decoded data signal into a number (P) of demultiplexed data signals, where M?2. The ADCs respectively receive the demultiplexed data signals. One of the ADCs is an (M+1)-bit ADC, and converts the corresponding demultiplexed data signal into a digital first decoded signal that contains an M-bits wide data portion and a one-bit wide error portion. Each of the other one(s) of the ADCs is an M-bit ADC, and converts the corresponding demultiplexed data signal into a digital second decoded signal that contains an M-bits wide data portion.

Abstract: A feed-forward equalizer (FFE) and a voltage-mode signal transmitter using the same are provided. The FFE includes an output, a plurality of tap drivers, and a control circuit. Each tap driver includes a cell driver. The control circuit includes a FFE control loop and an impedance control loop. The FFE control loop includes a first replica circuit corresponding to a part of the cell drivers. The FFE control loop generates at least one first reference voltage according to the first replica circuit. The impedance control loop includes a second replica circuit corresponding to the cell drivers in the tap drivers. The impedance control loop generates at least one second reference voltage according to the first reference voltage and the second replica circuit. The tap drivers are controlled by the first and second reference voltages to adjust respective output impedance thereof.

Abstract: An edge detector applied to a vertical-cavity surface-emitting laser is provided. The edge detector includes an alignment circuit, a rising-edge detecting circuit and a falling-edge detecting circuit. The alignment circuit is configured to receive and align multiple sets of differential input data and output multiple sets of differential output data corresponding to the multiple sets of differential input data. The multiple sets of differential output data include a set of delayed differential output data. The rising-edge detecting circuit is coupled to the alignment circuit. The rising-edge detecting circuit is configured to detect rising edges of the multiple sets of differential output data and output multiple sets of corresponding differential rising data. The falling-edge detecting circuit is coupled to the alignment circuit.

Abstract: A feed-forward equalizer (FFE) and a voltage-mode signal transmitter using the same are provided. The FFE includes an output, a plurality of tap drivers, and a control circuit. Each tap driver includes a cell driver. The control circuit includes a FFE control loop and an impedance control loop. The FFE control loop includes a first replica circuit corresponding to a part of the cell drivers. The FFE control loop generates at least one first reference voltage according to the first replica circuit. The impedance control loop includes a second replica circuit corresponding to the cell drivers in the tap drivers. The impedance control loop generates at least one second reference voltage according to the first reference voltage and the second replica circuit. The tap drivers are controlled by the first and second reference voltages to adjust respective output impedance thereof.

Abstract: A radio frequency transmitting device includes a frequency multiplier circuit, a mixer circuit, a power splitter, a plurality of phase shifting circuits, a plurality of amplifiers, and a plurality of antennas. The frequency multiplier circuit is configured to amplify a fundamental signal to generate a harmonic signal. The mixer circuit is configured to generate a RF signal based on an input signal and the harmonic signal. The power splitter is configured to generate a plurality of sub-RF signals. The phase shifting circuits are configured to shift the phase of the sub-RF signals. The amplifiers are configured to amplify the power of the sub-RF signals. The antennas are configured to transmit the sub-RF signals. Furthermore, a radio frequency receiving device is also disclosed herein.