Abstract: A microelectronic 3D packaging structure and a method of manufacturing the same are introduced. The microelectronic 3D packaging structure includes a first board with a plurality of a first edges and disposed with a first electronic device; a second board with a plurality of a second edges and disposed with a second electronic device, wherein at least one second edge of the second board is jointed to at least one first edge of the first board to form a joint line; and a joint connection portion disposed at the joint line of the two adjacent boards and adapted to function as a connection path for transmitting signals.

Abstract: A microelectronic 3D packaging structure and a method of manufacturing the same are introduced. The microelectronic 3D packaging structure includes a first board with a plurality of a first edges and disposed with a first electronic device; a second board with a plurality of a second edges and disposed with a second electronic device, wherein at least one second edge of the second board is jointed to at least one first edge of the first board to form a joint line; and a joint connection portion disposed at the joint line of the two adjacent boards and adapted to function as a connection path for transmitting signals.

Abstract: The present invention relates to a package structure, a packaging substrate and a chip. The package structure includes: a chip including a plurality of electrode pads on a surface thereof; a packaging substrate including a plurality of first conductive pads on a surface thereof; and a plurality of connecting units through which the electrode pads electrically communicate with the first conductive pads, in which the chip or the packaging substrate further includes a first surface finish layer over the electrode pads or the first conductive pads, and the first surface finish layer includes a Ni—Pd alloy layer. Accordingly, the surface finish method applied in a package structure, a packaging substrate and a chip has advantages of simple manufacture, low cost and high reliability.

Abstract: A MEMS-based fabrication process is disclosed to fabricate a hollow seamless drug-eluting stent. This stent fabrication process is characterized by using a photolithography process, a composite electroplating process, and a polishing process to mass-produce drug-eluting seamless stents. Combining a multi-layers photolithography process with a multi-layers composite electroforming process could make the formation of micro-holes, micro-caves, or micro-trenches integrated with this hollow seamless eluting-stent for any anti-thrombosis drug loading or filling.

Abstract: This invention is characteristic of combining an electroplating process with a polishing process to uniformly fabricate multi-layer flip chip copper pillar. All kinds of flip chip copper pillar with varied shapes and sizes are able to be defined by using multi-layer photolithography process commonly utilized in the semiconductor processes. After that, use both exposure and alignment procedures to accurately define multi-layer photoresist's patterns on the substrate. Some designated metallic materials are then electroplated on those completed well-defined patterns during the last photolithography process by means of an electroplating process. A polishing process follows the electroplating to level the rugged solder bumps, resulted from the impact on the certain changeable and inevitable electroplating parameters.