Abstract: An integrated circuit (IC) includes an oscillator circuit having a control input. A control circuit has a control output coupled to the control input. The control circuit is configured to generate a control signal to the control input of the oscillator circuit to cause: the oscillator circuit to be configured as a frequency-locked loop in response to the control signal being in a first state; and the oscillator circuit to be configured as a phase-locked loop in response to the control signal being in a second state.

Abstract: Disclosed are high-entropy oxides, and methods of their preparation. The high-entropy oxide is characterised by a sub-micron particle size and rod-like particle shape. The method of its preparation includes a co-precipitation step, preferably using an oxalate compound as a precipitating agent. Also disclosed are an electrode, e.g. an anode, a catalyst and an electrochemical cell comprising the high-entropy oxide.

Abstract: Provided are a vertical fatigue test device for a dynamic submarine cable based on a topology optimization design framework, and a method thereof. The device includes a bending table, a main framework, the dynamic submarine cable, a connecting hinge, a supporting frame, a bottom plate, and a tension actuator; the bending table is mounted on an upper plate at a top of the main framework, and the main framework, the supporting frame, and the tension actuator are mounted on the bottom plate; an upper end of the dynamic submarine cable is connected with the bending table through a clamping mechanism; each of a left end and a right end of the bending table is connected with a bending actuator; the bending actuators are connected to the upper plate and are configured to achieve reciprocating swinging of the bending table.

Abstract: An integrated circuit (IC) includes an oscillator circuit having a control input. A control circuit has a control output coupled to the control input. The control circuit is configured to generate a control signal to the control input of the oscillator circuit to cause: the oscillator circuit to be configured as a frequency-locked loop in response to the control signal being in a first state; and the oscillator circuit to be configured as a phase-locked loop in response to the control signal being in a second state.

Abstract: A method for predicting the fluctuation of circuit path delay on the basis of machine learning, comprising the following steps: S1: selecting suitable sample characteristics by means of analyzing the relationship between circuit characteristics and path delay; S2: generating a random path by means of enumerating values of randomized parameters, acquiring the maximum path delay by means of performing Monte Carlo simulation on the random path, selecting a reliable path by means of the 3? standard, and using the sample characteristics and path delay of the reliable path as a sample set (D); S3: establishing a path delay prediction model, and adjusting parameters of the model; S4: verifying the precision and stability of the path delay prediction model; S5: obtaining the path delay.

Abstract: A path delay prediction method for an integrated circuit based on feature selection and deep learning. First, an integrated feature selection method based on filter methods and wrapper methods is established to determine an optimal feature subset. Timing information and physical topological information of a circuit are then extracted to be used as input features of a model, and local physical and timing expressions of cells in circuit paths are captured by means of the convolution calculation mechanism of a convolutional neural network. In addition, a residual network is used to calibrate a path delay. Compared with traditional back-end design processes, the path delay prediction method provided by the invention has remarkable advantages in prediction accuracy and efficiency and has great significance in accelerating the integrated circuit design process.

Abstract: In an example, a system includes a buried Zener diode having a first terminal coupled to a voltage terminal. The system also includes a first resistor having a first terminal coupled to a second terminal of the buried Zener diode. The system includes a second resistor having a first terminal coupled to a second terminal of the first resistor. The system also includes a first transistor having a control terminal coupled to the first terminal of the second resistor. The system includes a second transistor having a control terminal coupled to a second terminal of the second resistor and an emitter coupled to an emitter of the first transistor. The system also includes a resistor network coupled to the second terminal of the first resistor, where the resistor network is configured to produce a reference voltage.

Abstract: A multi-wavelength laser system for thermal ablation in neurosurgery includes a magnetic resonance guidance unit, a laser ablation unit, and an optical fiber catheter unit. The laser ablation unit is configured to generate a surgical path and a surgical plan before a surgery, and regulate a plurality of laser modules and cooling modules in real time during the surgery to implement precision ablation of tissues, and the optical fiber catheter unit has a plurality of ablation channels and can implement ablation of a tumor of any scale. The multi-wavelength laser system allows for use of both a multi-wavelength treatment plan and a high-power single-wavelength single-channel treatment plan for precise conformal ablation on regular or irregular tumors, thereby greatly increasing the application range and use flexibility of the laser thermal therapy.

Abstract: A post-routing path delay prediction method for a digital integrated circuit is provided. First, physical design and static timing analysis are performed on a circuit by a commercial physical design tool and a static timing analysis tool, timing and physical information of a path is extracted before routing of the circuit to be used as input features of a prediction model, then the timing and physical correlation of all stages of cells in the path is captured by a transformer network, a predicted post-routing path delay is calibrated by a residual prediction structure, and finally, a final predicted post-routing path delay is output.

Abstract: An optimization method for a digital integrated circuit is provided. Under the precondition of satisfying certain timing constraints, circuit-level, path-level and gate cell-level features of a circuit are extracted to construct a leakage power optimization model, and optimization data from commercial circuit optimization tools is used to train the model to predict voltage threshold types of gate cells after circuit optimization, such that the circuit can be optimized by adjusting voltage thresholds of gate cells in a post-routing gate-level netlist, thus realizing the optimization objective of reducing leakage power.

Abstract: A path delay prediction method for an integrated circuit based on feature selection and deep learning. First, an integrated feature selection method based on filter methods and wrapper methods is established to determine an optimal feature subset. Timing information and physical topological information of a circuit are then extracted to be used as input features of a model, and local physical and timing expressions of cells in circuit paths are captured by means of the convolution calculation mechanism of a convolutional neural network. In addition, a residual network is used to calibrate a path delay. Compared with traditional back-end design processes, the path delay prediction method provided by the invention has remarkable advantages in prediction accuracy and efficiency and has great significance in accelerating the integrated circuit design process.

Abstract: An optimization method for a digital integrated circuit is provided. Under the precondition of satisfying certain timing constraints, circuit-level, path-level and gate cell-level features of a circuit are extracted to construct a leakage power optimization model, and optimization data from commercial circuit optimization tools is used to train the model to predict voltage threshold types of gate cells after circuit optimization, such that the circuit can be optimized by adjusting voltage thresholds of gate cells in a post-routing gate-level netlist, thus realizing the optimization objective of reducing leakage power.

Abstract: A post-routing path delay prediction method for a digital integrated circuit is provided. First, physical design and static timing analysis are performed on a circuit by a commercial physical design tool and a static timing analysis tool, timing and physical information of a path is extracted before routing of the circuit to be used as input features of a prediction model, then the timing and physical correlation of all stages of cells in the path is captured by a transformer network, a predicted post-routing path delay is calibrated by a residual prediction structure, and finally, a final predicted post-routing path delay is output.

Abstract: An air conditioning system, comprising an outdoor unit and an indoor heat exchange mechanism. The indoor heat exchange mechanism comprises an air conditioner indoor unit and a first heat exchange mechanism used for at least one among water cooling, water heating and space heating. The present air conditioning system integrates various functions into one, such as air-conditioning refrigeration, air-conditioning heating, producing household cold water, producing household hot water, and home heating by means of connecting indoor units for cooling and heating, a water cooling mechanism, a water heating mechanism and a device for floor heating located indoors to one outdoor unit. Moreover, the system directly utilizes high-temperature refrigerant to heat water for floor heating.

Abstract: A cooling sleeve includes an inner tube within which a bar-shaped or tubular object is placed to be cooled, and an outer tube within which the inner tube is located. The outer wall surface of the bar-shaped or tubular object contacts with the inner wall surface of the inner tube to form first contact portions, and axial gaps from the adjacent first contact portions form first circulation channels, and the inner wall surface of the outer tube contacts with the outer wall surface of the inner tube to form second contact portions, and axial gaps from the adjacent second contact portions form second circulation channels. Proximal ends of the first and second circulation channels are connected with each other inside the proximal end of the outer tube via a forming cavity, and distal ends of the first and second circulation channels are independently connected externally.

Abstract: The techniques and circuits, described herein, include solutions for auto-zeroing in auto-zero amplifiers in the presence of high frequency alternating current (AC) noise. In some aspects, first and second inputs of an auto-zero amplifier are coupled to a differential voltage with high AC noise. During an auto-zero phase, a first switching network decouples the inputs of a first amplifier, comprised within the auto-zero amplifier, from the differential voltage with high AC noise. In some examples, the inputs of the first amplifier may be connected to a regulated direct current (DC) voltage. The regulated DC voltage provides a more accurate auto-zero for the auto-zero amplifier, such that higher overall accuracy is achieved during an operation phase.

Abstract: The present disclosure provides a radiative cooling metal plate, a preparation method and application thereof. The radiative cooling metal plate includes a metal substrate, a first adhesive layer and a radiative cooling functional layer stacked in order, the radiative cooling functional layer is located on a surface of the metal substrate, the first adhesive layer is arranged between the metal substrate and the radiative cooling functional layer, and an elongation at break of the radiative cooling functional layer is in a range of 1% to 300%. The radiative cooling functional layer can have sufficient ductility, and can have sufficient deformation to cope with the bending of the radiative cooling functional layer during pressing, such that the radiative cooling functional layer will not be damaged or broken, thereby ensuring the structural integrity of the radiative cooling functional layer and great radiative cooling effect of the metal substrate.

Abstract: Disclosed in the present invention is a method for optimizing circuit timing based on a flexible register timing library.

Abstract: A deployable mesh antenna based on dome-type tensegrity includes: a wire mesh reflector, a dome-type reflector support system, and a peripheral deployable truss which are coaxially arranged; the peripheral deployable truss includes: a annular main rod and end-to-end truss units disposed on the main rod; an outermost cable boundary of the dome-type reflector support system is fixedly connected to the peripheral deployable truss, and the dome-type reflector support system includes: an inner strut ring, an outer circumference of the inner strut ring is connected to radial rib units, each radial rib unit is arranged at a radial direction of the inner strut ring, and the radial rib units are connected through hoop cables; the wire mesh reflector is covered on the dome-type reflector support system to form a parabolic structure, the wire mesh reflector is petal-shaped, and the wire mesh reflector has a grid structure.