Abstract: A method can include receiving, by a first controller component of a memory sub-system, a read operation, responsive to receiving the read operation, interrupting, by the first controller component, one or more program operations being performed by the memory sub-system, receiving, by the first controller component, a control sequence from a second controller component, wherein the control sequence is based on context data associated with the interrupted one or more program operations, and performing, by the first controller component, the control sequence by copying data of the interrupted one or more program operations from a first memory location to a second memory location of a memory component associated with the memory sub-system, and performing the read operation.

Abstract: Methods, systems, and devices for full multi-plane operation enablement are described. A flash controller can determine that a first plane of a set of planes of a memory die is an invalid plane. The flash controller can issue a single descriptor associated with a multi-plane operation for the set of planes of the memory die. The single descriptor can include a plurality of commands for the multi-plane operation in which the first command of the plurality of commands can be a duplicate of a second command of the plurality of commands based on the first plane being the invalid plane. In some cases, a negative-and (NAND) controller can receive the single descriptor associated with the multi-plane operation for the set of planes of a memory die. The NAND controller can issue a plurality of commands for the multi-plane operation based on receiving the single descriptor.

Abstract: Methods, systems, and devices for full multi-plane operation enablement are described. A flash controller can determine that a first plane of a set of planes of a memory die is an invalid plane. The flash controller can issue a single descriptor associated with a multi-plane operation for the set of planes of the memory die. The single descriptor can include a plurality of commands for the multi-plane operation in which the first command of the plurality of commands can be a duplicate of a second command of the plurality of commands based on the first plane being the invalid plane. In some cases, a negative-and (NAND) controller can receive the single descriptor associated with the multi-plane operation for the set of planes of a memory die. The NAND controller can issue a plurality of commands for the multi-plane operation based on receiving the single descriptor.

Abstract: A method can include receiving, by a first controller component of a memory sub-system, a read operation, responsive to receiving the read operation, interrupting, by the first controller component, one or more program operations being performed by the memory sub-system, receiving, by the first controller component, a control sequence from a second controller component, wherein the control sequence is based on context data associated with the interrupted one or more program operations, and performing, by the first controller component, the control sequence by copying data of the interrupted one or more program operations from a first memory location to a second memory location of a memory component associated with the memory sub-system, and performing the read operation.

Abstract: An indication that one or more program operations have been interrupted as a result of a read operation can be received at a first controller component associated with a memory sub-system. Context data associated with interrupted program operations can be received at the first controller component. A control sequence based on the context data can be generated at the first controller component. The control sequence can indicate how a second controller component associated with the memory sub-system interacts with a memory component of the memory sub-system to perform the read operation and to resume the interrupted program operations. The control sequence can further specify one or more additional operations that are associated with copying data of the interrupted program operations between first and second memory locations of the memory component. The control sequence can be provided to the second controller component.

Abstract: Methods, systems, and devices for full multi-plane operation enablement are described. A flash controller can determine that a first plane of a set of planes of a memory die is an invalid plane. The flash controller can issue a single descriptor associated with a multi-plane operation for the set of planes of the memory die. The single descriptor can include a plurality of commands for the multi-plane operation in which the first command of the plurality of commands can be a duplicate of a second command of the plurality of commands based on the first plane being the invalid plane. In some cases, a negative-and (NAND) controller can receive the single descriptor associated with the multi-plane operation for the set of planes of a memory die. The NAND controller can issue a plurality of commands for the multi-plane operation based on receiving the single descriptor.

Abstract: A checkout apparatus for barcodeless merchandise, the checkout apparatus includes an image camera module and a control module coupled to the image camera module. The image camera module obtains a merchandise image includes the barcodeless merchandise. The control module receives the merchandise image and generates an output datum according to a result of a merchandise identification program after the control module performs the merchandise identification program on the merchandise image. At least one of the image camera module and the control module is coupled to the point of sales (POS) management system or is embedded in the POS management system, the output datum is readable for the POS management system.

Abstract: An indication that one or more program operations have been interrupted as a result of a read operation can be received at a first controller component associated with a memory sub-system. Context data associated with interrupted program operations can be received at the first controller component. A control sequence based on the context data can be generated at the first controller component. The control sequence can indicate how a second controller component associated with the memory sub-system interacts with a memory component of the memory sub-system to perform the read operation and to resume the interrupted program operations. The control sequence can further specify one or more additional operations that are associated with copying data of the interrupted program operations between first and second memory locations of the memory component. The control sequence can be provided to the second controller component.

Abstract: A read operation can be received while one or more program operations are being performed at a memory sub-system. In response to receiving the read operation, the one or more program operations being performed at the memory sub-system can be interrupted. Context data associated with the one or more interrupted program operations can be determined and the context data can be provided to a firmware associated with the memory sub-system. A control sequence can be received from the firmware based on the context data. The read operation can be performed and the one or more interrupted program operations can be resumed based on the control sequence from the firmware.

Abstract: A read operation can be received while one or more program operations are being performed at a memory sub-system. In response to receiving the read operation, the one or more program operations being performed at the memory sub-system can be interrupted. Context data associated with the one or more interrupted program operations can be determined and the context data can be provided to a firmware associated with the memory sub-system. A control sequence can be received from the firmware based on the context data. The read operation can be performed and the one or more interrupted program operations can be resumed based on the control sequence from the firmware.

Abstract: A superimposition device of virtual guiding indication and reality image includes at least an image capturing device, a processor, a graphic processing unit (GPU), and a display device. The image capturing device captures reality image including instant scene. The processor receives the reality image and obtains height variation information. The GPU performs image correction processing on the reality image to obtain corrected image, generates updated transformation matrix according to the height variation information, and performs inverse perspective projection transformation by using the updated transformation matrix to generate bird's-eye view image of the corrected image and superimposes virtual guiding indication on the bird's-eye view image and performs perspective projection transformation on the bird's-eye view image to transform the bird's-eye view image into three-dimensional (3D) navigation image which includes the guiding indication.

Abstract: A graphene-based composite structure is disclosed. The graphene-based composite structure includes a graphene layer, a transition metal layer, and a substrate. The graphene layer, transition metal layer, and substrate are stacked together in series to form a sandwich structure. The graphene layer and the transition metal layer are coupled by d-p orbitals hybridization. The transition metal layer and the substrate are also coupled by d-p orbitals hybridization. A method for making graphene-based composite structure is also disclosed.

Abstract: A graphene-based composite structure is disclosed. The graphene-based composite structure includes a graphene layer, a transition metal layer, and a substrate. The graphene layer, transition metal layer, and substrate are stacked together in series to form a sandwich structure. The graphene layer and the transition metal layer are coupled by d-p orbitals hybridization. The transition metal layer and the substrate are also coupled by d-p orbitals hybridization. A method for making graphene-based composite structure is also disclosed.

Abstract: A variable frequency decoding apparatus operable in a portable audio device that can improve the power management is disclosed. The above apparatus has a decoder and a clock generator that provides the system clock for the decoder. When a bit stream representing audio compressed data is received, the decoder simultaneously provides the audio information embedded in the audio compressed data such as the bit rate and the sampling frequency of the data frame to the clock generator, and then the clock generator adjusts the clock signals; which are used by the decoder to restore to the original PCM format, to match the audio information embedded in the data frame. This audio signal compression technique can prevent possible output delay and reduce power consumption as compared with the conventional way that used a fixed sys clock.

Abstract: A program redirection and modification method for embedded processors with a limited amount of SRAM sets at least one address in a program of ROM to an origin address of at least one register. To redirect the embedded processor to execute another section in the program in ROM or SRAM, a destination address of the register is set to another address of the program in ROM or a program in the SRAM. Therefore, the embedded processor sets the addresses in the register and then the program in ROM can debugged or extended to an external program.

Abstract: A method of improving performance and power utilization of portable a CD player with an electronic anti-shock system (EASS) is disclosed. When PCM signals are received by the EASS, the audio signals are compressed with a high compression rate algorithm and saved in a temporary memory, and later when the audio data are read out from the temporary memory, the audio data are decoded with the same audio compression algorithm to restore to the original PCM format, thus a data buffering is created between the reading of data and the playback of sound. A high compression rate algorithm can increase the utilization of DRAM memory and lengthen the buffering time considerably. The present invention has incorporated an audio compression algorithm having high compression rate in the EASS to attain the most desirable balance point between audio performance, power management, and costs.

Abstract: A method of optimizing the compression rate in Adaptive Differential Pulse Code Modulation (ADPCM) is disclosed. The modified pulse code modulation technique employs a prognostic code converter to generate variable length codes on top of the ADPCM coding, based on the probability of occurrence of data bits in a data sample. This variable-length coding is able to further reduce the compressed data size by increasing the compression rate of the conventional ADPCM coding.

Abstract: A thermal control system for variable speed microprocessor with a piecewise estimate of temperature change. The estimate is modeled after actual temperature change measurements of a microprocessor operating at low and high speeds and is recorded in a digital format in storage registers, one set of registers for each operating frequency. A counter counts sample microprocessor clock signals for a time over which the microprocessor speed is operating at a specific speed and provides a basic count signal. This basic count signal is incremented or decremented by comparison with stored values of the piecewise estimate of temperature change. As the basic signal increases or decreases, new slopes are provided to the counter for adjusting the basic count, upwards or downwards, depending on whether the system speed is high, intermediate or low. The adjusted counter output is also fed to comparators, which monitor a desired upper and lower temperature limit.