Patents by Inventor Peng Cheng Lin

Peng Cheng Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240391049
    Abstract: A planarization tool is configured to monitor and analyze the condition of a polishing pad over the life of the polishing pad. A piezoelectric pad monitoring device may be mounted to a polishing head of the planarization tool in place of a semiconductor wafer. The piezoelectric pad monitoring device may be pressed against the polishing pad. When pressed against the polishing pad, the piezoelectric pad monitoring device may generate a signal based on a quantity of pad contacts, on the polishing pad, that are in contact with the piezoelectric pad monitoring device. The signal may be provided to a processor of the planarization tool so that the processor may generate, based on the signal, a map of the pad contacts on the polishing pad. The processor may use the map of the pad contacts to determine properties of the polishing pad such as roughness and/or uniformity, among other examples.
    Type: Application
    Filed: May 25, 2023
    Publication date: November 28, 2024
    Inventors: Yi-Cheng LIN, Kao-Feng LIAO, Peng-Chung JANGJIAN
  • Publication number: 20140177188
    Abstract: This disclosure provides systems, methods and apparatus for packaging of dissimilar devices using electromagnetic radiation from a laser. In one aspect, an apparatus can include a first substrate, a second substrate, and a first device and a second device disposed on the second substrate. A first metal ring on the first substrate contacts a second metal ring on a second substrate, and is heated by a first electromagnetic radiation from a laser to enclose a first cavity containing the first device. A third metal ring on the first substrate contacts a fourth metal ring on the second substrate, and is heated by a second electromagnetic radiation to enclose a second cavity containing the second device. Enclosing the first cavity may be performed under a first atmosphere, and the enclosing the second cavity may be performed under a second, different atmosphere.
    Type: Application
    Filed: December 26, 2012
    Publication date: June 26, 2014
    Applicant: QUALCOMM MEMS TECHNOLOGIES, INC.
    Inventors: Philip Jason Stephanou, Ravindra V. Shenoy, Kwan-Yu Lai, James G. Shook, Nassim Khonsari, Peter Jings Lin, Tsongming Kao, Peng Cheng Lin
  • Patent number: 8724038
    Abstract: This disclosure provides systems, methods and apparatus for a combined sensor device. In some implementations, a combined sensor device includes a wrap-around configuration wherein an upper flexible substrate has patterned conductive material on an extended portion to allow routing of signal lines, electrical ground, and power. One or more integrated circuits or passive components, which may include connecting sockets, may be mounted onto the flexible layer to reduce cost and complexity. Such implementations may eliminate a flex cable and may allow a bezel-less configuration.
    Type: Grant
    Filed: October 11, 2011
    Date of Patent: May 13, 2014
    Assignee: QUALCOMM MEMS Technologies, Inc.
    Inventors: Srinivasan Kodaganallur Ganapathi, Nicholas Ian Buchan, Kurt Edward Petersen, Ravindra V. Shenoy, Peng Cheng Lin, Ericson Cheng
  • Publication number: 20130032385
    Abstract: This disclosure provides systems and methods for forming a metal thin film shield over a thin film cap to protect electromechanical systems devices in a cavity beneath. In one aspect, a dual or multi layer thin film structure is used to seal a electromechanical device. For example, a metal thin film shield can be mated over an oxide thin film cap to encapsulate the electromechanical device and prevent degradation due to wafer thinning, dicing and package assembly induced stresses, thereby strengthening the survivability of the electromechanical device in the encapsulated cavity. During redistribution layer processing, a metal thin film shield, such as a copper layer, is formed over the wafer surface, patterned and metalized.
    Type: Application
    Filed: August 3, 2011
    Publication date: February 7, 2013
    Applicant: QUALCOMM MEMS Technologies, Inc.
    Inventors: Peng Cheng Lin, Mario Francisco Velez
  • Publication number: 20120092350
    Abstract: This disclosure provides systems, methods and apparatus for a combined sensor device. In some implementations, a combined sensor device includes a wrap-around configuration wherein an upper flexible substrate has patterned conductive material on an extended portion to allow routing of signal lines, electrical ground, and power. One or more integrated circuits or passive components, which may include connecting sockets, may be mounted onto the flexible layer to reduce cost and complexity. Such implementations may eliminate a flex cable and may allow a bezel-less configuration.
    Type: Application
    Filed: October 11, 2011
    Publication date: April 19, 2012
    Applicant: QUALCOMM MEMS TECHNOLOGIES, INC.
    Inventors: Srinivasan Kodaganallur Ganapathi, Nicholas Ian Buchan, Kurt Edward Petersen, Ravindra V. Shenoy, Peng Cheng Lin, Ericson Cheng
  • Publication number: 20110254758
    Abstract: Various embodiments described herein involve making connections with the display leads on more than one side of the display array, e.g., on 2 sides, 3 sides or all 4 sides of the display array. By making connections with the display leads on more than one side of the display array, the available area for bonding leads and control circuitry may be increased. The driver chip(s), discrete components, and other active components necessary for addressing the display panel may be attached to the top or the bottom of a flexible printed circuit (“FPC”) or a similar device. Some embodiments involve attaching an FPC to the display such that that the backplate is substantially encased by the FPC.
    Type: Application
    Filed: April 19, 2010
    Publication date: October 20, 2011
    Applicant: QUALCOMM MEMS TECHNOLOGIES, INC.
    Inventors: Peng Cheng Lin, Mithran Cheriyan Mathew
  • Patent number: 7643305
    Abstract: Stiffeners in are provided in a flexible printed circuit to prevent damages to leads and traces of the flexible circuit caused by bending, folding and other stresses.
    Type: Grant
    Filed: March 7, 2008
    Date of Patent: January 5, 2010
    Assignee: QUALCOMM MEMS Technologies, Inc.
    Inventor: Peng Cheng Lin
  • Publication number: 20090323170
    Abstract: An improved substrate or cover plate design with a groove for effective singulation of individual display apparatus. In one embodiment, the display apparatus comprises a prefabricated groove on an inside face of a substrate or cover plate to facilitate separation of a MEMS device from a plurality of MEMS devices formed a substrate. In some embodiments, the prefabricated grooves make breaking at pseudo scribe lines simple by thinning and weakening the substrate or cover plate at a scribe zone and act as an improved guide for breaking. Scribe cut relief preserves components, structural integrity, and produces a clean break without inducing excessive or unwanted stresses into the MEMS core and ensures no damage at the panel ledge for subsequent interconnect assembly.
    Type: Application
    Filed: June 30, 2008
    Publication date: December 31, 2009
    Applicant: QUALCOMM MEMS Technologies, Inc.
    Inventor: Peng Cheng Lin
  • Publication number: 20090231816
    Abstract: Stiffeners in are provided in a flexible printed circuit to prevent damages to leads and traces of the flexible circuit caused by bending, folding and other stresses.
    Type: Application
    Filed: March 7, 2008
    Publication date: September 17, 2009
    Applicant: QUALCOMM MEMS Technologies, Inc.
    Inventor: Peng Cheng Lin
  • Patent number: 6452790
    Abstract: A method for installing memory into a computer module. The method includes providing a used computer module, which comprises a housing to enclose a hard disk drive, a memory module for random access memory devices and a central processing unit coupled to the hard disk drive and coupled to the random access memory. The method also includes removing a top cover from a base of the housing to expose the hard disk drive and the memory module. Thereafter, the hard disk drive is removed from the base of the housing and a second hard disk drive is inserted onto the base. The top cover is reattached to the base of the housing to complete the installation process.
    Type: Grant
    Filed: July 5, 2000
    Date of Patent: September 17, 2002
    Assignee: Acquis Technology, Inc.
    Inventors: William W. Y. Chu, Tony Man, Peng Cheng Lin
  • Patent number: 5901043
    Abstract: In semiconductor packaging, a method and device for reducing thermal stress on a die and for reinforcing the strength of a die. A thermally-conductive member is positioned in a cooperating manner with the die during the packaging process.
    Type: Grant
    Filed: August 3, 1994
    Date of Patent: May 4, 1999
    Assignee: National Semiconductor Corporation
    Inventors: Peng-Cheng Lin, Hem P. Takiar
  • Patent number: 5504370
    Abstract: An electronic system circuit package is disclosed herein. The package utilizes a lead frame having an electrically conductive component support segment incorporating provisions for mounting a plurality of electronic components directly on the support segment in accordance with a predetermined circuit design. The circuit package is then encapsulated in a dielectric medium. In a preferred embodiment, at least some of the electronic components are mounted directly to electrically isolated subsegments of the component support segment and electrically interconnected through their respective subsegments to other components.
    Type: Grant
    Filed: September 15, 1994
    Date of Patent: April 2, 1996
    Assignee: National Semiconductor Corporation
    Inventors: Peng-Cheng Lin, Hem P. Takiar
  • Patent number: 5502289
    Abstract: A circuit assembly which includes a semiconductor die having substantially parallel opposing first and second surfaces and at least one electrical contact mounted on the first surface. A first element having substantially parallel opposing first and second surfaces and at least one electrical contact mounted on one of its surfaces is mounted on and at least partially supported at its second surface by the first surface of the semiconductor die. The first element is positioned such that the semiconductor die electrical contact is exposed. A fine wire conductor having first and second ends is connected at its first end to either the semiconductor die electrical contact or the first element electrical contact. A method of manufacturing this circuit assembly is also disclosed.
    Type: Grant
    Filed: March 13, 1995
    Date of Patent: March 26, 1996
    Assignee: National Semiconductor Corporation
    Inventors: Hem P. Takiar, Peng-Cheng Lin
  • Patent number: 5495398
    Abstract: A circuit assembly which includes a semiconductor die having substantially parallel opposing first and second surfaces and at least one electrical contact mounted on the first surface. A first element having substantially parallel opposing first and second surfaces and at least one electrical contact mounted on one of its surfaces is mounted on and at least partially supported at its second surface by the first surface of the semiconductor die. The first element is positioned such that the semiconductor die electrical contact is exposed. A fine wire conductor having first and second ends is connected at its first end to either the semiconductor die electrical contact or the first element electrical contact. A method of manufacturing this circuit assembly is also disclosed.
    Type: Grant
    Filed: June 5, 1995
    Date of Patent: February 27, 1996
    Assignee: National Semiconductor Corporation
    Inventors: Hem P. Takiar, Peng-Cheng Lin
  • Patent number: 5491360
    Abstract: An electric packaging arrangement for isolated circuits is described. A lead frame is formed with at least one off-centered tie bar connected between one of the circuits on the lead frame's internal lead and an external handling side rail. The tie bar is off-centered by a specified distance from the longitudinal center line of the package. The external side rail is used to support and align the lead frame during manufacturing. To meet safety requirements, such as the UL-1950 requirements, electrical components in a primary circuit and a secondary circuit are attached and electrically coupled to the lead frame in a manner such that the smallest internal distance between internal circuits is at least a predefined distance. The external distance between the tie bar, connected to the secondary circuit, and the closest primary circuit pin is set to meet external circuit component spacing requirements for isolated circuits.
    Type: Grant
    Filed: December 28, 1994
    Date of Patent: February 13, 1996
    Assignee: National Semiconductor Corporation
    Inventor: Peng-Cheng Lin
  • Patent number: 5428245
    Abstract: A lead frame for use in an integrated circuit package is disclosed herein. The lead frame includes a magnetic component winding wherein the winding is formed as an integral part of the lead frame. Additional windings may be formed as an integral part of the lead frame and then folded into position over the first winding to form a multiple layered magnetic component winding. In one embodiment, the lead frame based winding is coated with a magnetic material to form a lead frame based inductor. There is also disclosed a method of producing a lead frame including a magnetic component winding wherein the winding is formed as an integral part of the lead frame.
    Type: Grant
    Filed: May 6, 1994
    Date of Patent: June 27, 1995
    Assignee: National Semiconductor Corporation
    Inventors: Peng-Cheng Lin, Seth R. Sanders, Hem P. Takiar
  • Patent number: 5422435
    Abstract: A circuit assembly which includes a semiconductor die having substantially parallel opposing first and second surfaces and at least one electrical contact mounted on the first surface. A first element having substantially parallel opposing first and second surfaces and at least one electrical contact mounted on one of its surfaces is mounted on and at least partially supported at its second surface by the first surface of the semiconductor die. The first element is positioned such that the semiconductor die electrical contact is exposed. A fine wire conductor having first and second ends is connected at its first end to either the semiconductor die electrical contact or the first element electrical contact. A method of manufacturing this circuit assembly is also disclosed.
    Type: Grant
    Filed: May 22, 1992
    Date of Patent: June 6, 1995
    Assignee: National Semiconductor Corporation
    Inventors: Hem P. Takiar, Peng-Cheng Lin, Luu T. Nguyen
  • Patent number: 5415331
    Abstract: The invention provides a method and apparatus for picking a separated semiconductor die 128 from a wafer and placing it on a die attach pad 144 for bonding thereto. In a preferred embodiment, the apparatus comprises a die collet having a body 124 with a proximal end 123 and a distal end 125; at least one pair of spaced-apart walls 136 extending distally from the distal end of the body and having opposing faces 181 defining an aperture 126, the faces of the walls being sloped such that a distal portion of the aperture is wider than the die and a proximal portion of the aperture is narrower than the die; a recess 152 on the faces of the walls extending substantially the length of the die, the recess having a distally-facing surface 154 for contacting at least a portion of the top side 138 of the die; and means for holding the die in the aperture, usually including a vacuum port 128.
    Type: Grant
    Filed: July 8, 1994
    Date of Patent: May 16, 1995
    Assignee: National Semiconductor Corporation
    Inventor: Peng-Cheng Lin
  • Patent number: 5348316
    Abstract: The invention provides a method and apparatus for picking a separated semiconductor die 128 from a wafer and placing it on a die attach pad 144 for bonding thereto. In a preferred embodiment, the apparatus comprises a die collet having a body 124 with a proximal end 123 and a distal end 125; at least one pair of spaced-apart walls 136 extending distally from the distal end of the body and having opposing faces 181 defining an aperture 126, the faces of the walls being sloped such that a distal portion of the aperture is wider than the die and a proximal portion of the aperture is narrower than the die; a recess 152 on the faces of the walls extending substantially the length of the die, the recess having a distally-facing surface 154 for contacting at least a portion of the top side 138 of the die; and means for holding the die in the aperture, usually including a vacuum port 128.
    Type: Grant
    Filed: July 16, 1992
    Date of Patent: September 20, 1994
    Assignee: National Semiconductor Corporation
    Inventor: Peng-Cheng Lin
  • Patent number: 5339216
    Abstract: In semiconductor packing, a method and device for reducing thermal stress on a die and for reinforcing the strength of a die, A thermally-conductive member is positioned in a cooperating manner with the die during the packaging process.
    Type: Grant
    Filed: March 2, 1993
    Date of Patent: August 16, 1994
    Assignee: National Semiconductor Corporation
    Inventors: Peng-Cheng Lin, Hem P. Takiar