Abstract: Described are compounds of the structure R4-a—Si-((Sp-Y)—Zb)a, wherein “a” is an integer from 1 to 3; “b” is an integer from 0 to (3×a); “Z,” which is absent when “b”=0, is halogen, C1-6 linear or branched alkyl, alkenyl, or alkynyl, C1-6 linear or branched halo-alkyl, halo-alkenyl, or halo-alkynyl, or wherein each “R” is halogen, C1-6 linear or branched alkyl, alkenyl, or alkynyl or C1-6 linear or branched halo-alkyl, halo-alkenyl, or halo-alkynyl; each “Sp” C1-15 linear or branched alkylenyl or C1-15 linear or branched halo-alkylenyl; and each “Y” an organic polar group. Also described are electrolyte compositions containing one or more of these compounds.

Abstract: The present disclosure provides a liquid crystal display device where a width of each of the branch electrodes of one of the main pixel electrode and the secondary pixel electrode of each of the blue pixel units is less than the width of the each of the branch electrodes of the one of the main pixel electrode and the secondary pixel electrode of the each of the red pixel units and the green pixel units, and a width of each of the branch electrodes of another of the main pixel electrode and the secondary pixel electrode of each of the blue pixel units is less than the width of the each of the branch electrodes of the another of the main pixel electrode and the secondary pixel electrode of the each of the red pixel units and the green pixel units.

Abstract: An embedded gateway system includes a processor, a first memory, a second memory, and a data prefetch circuit. The processor is used to execute a first program. The first memory is used to store a first data. The first memory and the second memory are external memories of the processor, and access latency of the second memory is lower that access latency of the first memory. The data prefetch circuit is used to perform a first data prefetch operation upon the first memory for reading a first prefetched data from the first memory and writing the first prefetched data into the second memory. Before a time point at which the processor executes a data access code segment of the first program to access the first data, the first data prefetch operation reads the first data from the first memory as the first prefetched data.

Abstract: A network packet processing apparatus includes a receive (RX) ring buffer, a transmit (TX) ring buffer, a plurality of queues, a plurality of first processor cores, and a second processor core. The first processor cores read a plurality of groups of RX packet descriptors in turn according to a polling order, and perform parallel processing upon a plurality of groups of packets. Each first processor core generates at least one TX packet descriptor and at least one queue element for a group of packets, and pushes the at least one queue element into a corresponding queue, where the at least one queue element has an end flag asserted therein. The second processor core reads the queues in turn according to the polling order. When reading the end flag, the second processor core switches to read a next queue according to the polling order.

Abstract: Provided is a light source device, including a first light source module configured to output a first light beam; a second light source module configured to output a second light beam, etendue of the first light beam being smaller than etendue of the second light beam; a polarization conversion system configured to receive the first light beam and the second light beam and perform polarization conversion on at least one of the first light beam the second light beam; and an etendue increasing module provided on a light path between the first light source module and the polarization conversion system and configured to increase the etendue of the first light beam. Etendue of the first light beam incident on the PCS increases and the optical power density of the first light beam incident on the PCS decreases, thereby preventing overheating from affecting reliability of the polarization conversion system.

Abstract: A resource management apparatus includes a processor, a resource management circuit, and a second memory. The processor includes an internal memory. The resource management circuit includes a first memory, wherein an access speed of the first memory is higher than an access speed of the second memory. The resource management circuit is arranged to load a plurality of first resource identifiers stored in the second memory into the first memory, and return a plurality of second resource identifiers stored in the first memory to the second memory. The resource management circuit is further arranged to load a plurality of third resource identifiers stored in the first memory into the internal memory, and return a plurality of fourth resource identifiers stored in the internal memory to the first memory.

Abstract: A positive electrode material is obtained by mixing a lithium manganese iron phosphate material and a ternary material. During mixing, a mass ratio n of the ternary material to the lithium manganese iron phosphate material in the positive electrode material is determined according to a range of a ratio k of an actual specific capacity of the ternary material to an actual specific capacity of the lithium manganese iron phosphate material. Specifically, when k is less than or equal to 1.34, n is 1 to 9; and when k is greater than 1.34, n is 0.1 to 1.

Abstract: A network packet processing apparatus includes a receive (RX) ring buffer, a transmit (TX) ring buffer, and a plurality of first processor cores. The RX ring buffer includes a plurality of storage blocks, each arranged to buffer an RX packet descriptor of a network packet before the network packet is processed. The TX ring buffer includes a plurality of storage blocks, each arranged to buffer a TX packet descriptor of the network packet after the network packet is processed. The first processor cores retrieve RX packet descriptors of a plurality of network packets from the RX ring buffer in parallel, process the plurality of network packets in parallel, and write TX packet descriptors of the plurality of network packets into the TX ring buffer in parallel.

Abstract: A microphone control system includes: a first switch and an audio processor; wherein a first selection terminal of the first switch is configured to be connected to a first microphone; a second selection terminal of the first switch is configured to be connected to a second microphone; a common terminal of the first switch is connected to a first microphone interface of the audio processor; the first switch is configured to receive a first switching control signal, under control of which the first selection terminal is connected to the common terminal to send a first audio signal received by the first microphone to the audio processor; and the first switch is further configured to receive a second switching control signal, under control of which the second selection terminal is connected to the common terminal to send a second audio signal received by the second microphone to the audio processor.

Abstract: A speech interaction device, apparatus, method, cloud sever and medium are provided. The speech interaction device includes, a speech processor, a first communication module, at least one microphone and a speech interaction system, where the speech interaction system includes a second communication module. A first input terminal of the speech processor is connected with the microphone, a first output terminal of the speech processor is connected with the first communication module, and the speech processor is configured to determine that the microphone obtains a first speech signal, establish a connection with a cloud server through the first communication module, and send the first speech signal obtained by the microphone to the cloud server. The speech interaction system is connected with the cloud server through the second communication module, and the speech interaction system is configured to receive a first response signal sent by the cloud server for speech interaction.

Abstract: Disclosed are a color correction method for a lighting system and a lighting system, the lighting system includes a first laser set (10), a second laser set (20), a driving assembly (30), a wavelength conversion device (40), and a light-combining assembly (50), where the first laser set (10) is used for emitting first primary light; the second laser set (20) is used for emitting second primary light; the driving assembly (30) is used for driving the first laser set (10) to emit the first primary light in a first timing sequence and a second timing sequence, and driving the second laser set (20) to emit the second primary light in the first timing sequence and the second timing sequence; the wavelength conversion device (40) is used for converting the first primary light into converted light in the second timing sequence; and the light-combining assembly (50) is used for combining the first primary light and the second primary light in the first timing sequence, and combining the second primary light and the c

Abstract: A display panel is provided. In a plan view of the display panel, the black matrix layer covers the first connection portion and the second connection portion, and the second common electrode and the pixel portion are in an area of the opening, where an angle formed between an extension direction of the first connection portion and an extension direction of the first branch electrode is greater than or equal to 120 degrees and less than 180 degrees, or the extension direction of the first connection portion coincides with the extension direction of the first branch electrode.

Abstract: An electronic device includes one or more processors comprising processing circuitry, and memory comprising one or more storage media storing instructions that, when executed individually or collectively by the one or more processors, cause the electronic device to determine a first spectrum comprising a plurality of frequency components for an image containing noise determined at each of a plurality of levels by transforming the image into a frequency domain at the plurality of levels, determine a plurality of tokens for a plurality of patches by segmenting the first spectrum into the plurality of patches and encoding the plurality of patches based on positions of corresponding patches, denoise the plurality of tokens based on the image, determine a second spectrum obtained by denoising the first spectrum, based on the plurality of denoised tokens, and generate a high-resolution (HR) image with an increased resolution of the image by inversely transforming the second spectrum into a spatial domain at the plu

Abstract: A network packet processing device includes a parallel processing circuit, a packet dispatch circuit and a packet order-preserving processing circuit. The parallel processing circuit includes a plurality of packet processing circuits for processing different packets in parallel. Each packet processing circuit includes a network processing unit (NPU) core. The packet dispatch circuit distributes the packets to the packet processing circuits, respectively. The packet order-preserving processing circuit performs an order-preserved sending operation upon a plurality of processed packets generated by the parallel processing circuit, wherein the processed packets include first and second processed packets corresponding to first and second packets in the packets, respectively, and an order of the first and second processed packets in an output flow sent from the packet order-preserving processing circuit is the same as an order of the first and second packets in an input flow received by the packet dispatch circuit.

Abstract: An apparatus includes one or more processors comprising processing circuitry, and memory comprising one or more storage media storing instructions that, when executed individually or collectively by the one or more processors, cause the apparatus to generate a feature map from an input image, generate a coordinate combined feature map by concatenating the feature map and a coordinate map indicating a location of a feature point of the feature map, predict noise of the feature map using a noise prediction model, based on the coordinate combined feature map, generate a denoised feature map by denoising the feature map based on the predicted noise, and generate a target image based on the denoised feature map.

Abstract: The present disclosure provides an extended reality device and a control method thereof. The extended reality device includes: a front part and a rear part; the front part comprising: a display module, configured to display extended reality image; the rear part comprising: a system controller connected to the display module and configured to control operation of the display module; a battery connected to the system controller and configured to supply power to each electrical device. Through the above solution, transferring the system controller and the battery to the rear part setting, so that the weight of the front part of the extended reality device is significantly reduced, the thickness of the front part is significantly reduced, the weight of the rear part and the front part can be balanced, there is no bias when user wears the extended reality device, which improves the user's wearing comfort.

Abstract: A network packet processing device includes a hardware-accelerated forwarding circuit and a network processing unit (NPU). The hardware-accelerated forwarding circuit is used to receive a plurality of L4S packets from a network port and send the plurality of L4S packets to another network port through hardware-accelerated forwarding without intervention of a central processing unit (CPU). The NPU is used to perform ECN marking on at least a portion of the plurality of L4S packets.

Abstract: Array substrates and display panels are provided in the present application provides. By the gradually decreased width of at least one portion of the branch electrodes in the array substrate along the direction from a position near a connection between the branch electrodes and the main electrode to a position away from the connection between the branch electrodes and the main electrodes, at least one region having different electric field intensities at various positions thereof is presented in the array substrate, which therefore causes the deflection angle of the liquid crystal distinctive at various positions of the at least one region. Consequently, a viewing angle effect from 8-domain can be achieved based on a 4-domain design, providing a display effect with a wide viewing angle at a low gray scale and a high transmittance at a high gray scale and compromising the wide viewing angle with a high aperture ratio.

Abstract: The present disclosure provides a liquid crystal display device where a width of each of the branch electrodes of one of the main pixel electrode and the secondary pixel electrode of each of the blue pixel units is less than the width of the each of the branch electrodes of the one of the main pixel electrode and the secondary pixel electrode of the each of the red pixel units and the green pixel units, and a width of each of the branch electrodes of another of the main pixel electrode and the secondary pixel electrode of each of the blue pixel units is less than the width of the each of the branch electrodes of the another of the main pixel electrode and the secondary pixel electrode of the each of the red pixel units and the green pixel units.

Abstract: The present application provides a liquid crystal display panel and a liquid crystal display device. The liquid crystal display panel makes the second capacitor of the first sub-pixel greater than the second capacitor of the second sub-pixel and connects a drain electrode to a pixel electrode such that a ratio of the first capacitor of the first sub-pixel in a capacitor formed by and connected to the pixel electrode is similar to or even the same as a ratio of the first capacitor of the second sub-pixel in the capacitor formed by and connected to the pixel electrode, which avoids issues of display crosstalk and afterimage.