Abstract: Systems and methods for machine learning (ML) based electronic document completion are described. A system is configured to receive one or more electronic documents to be completed for a user and provide the one or more electronic documents to an ML model. The ML model is trained to categorize the one or more electronic documents based on previously categorized electronic documents. The system is also configured to: categorize, for each electronic document of the one or more electronic documents, the electronic document into an electronic document category by the ML model; identify one or more fields to be entered by the user based on categorizing the one or more electronic documents; generate a dynamic form including the one or more fields to be entered; and provide the dynamic form for display to the user. Identifying the one or more fields to be entered may be based on a statistical model.

Abstract: Techniques are disclosed for a bi-directional notification service. The techniques disclosed herein notify a user of an application in real-time based on a context of the application. A given notification may require a particular context before the notification can be presented to the user. The notification service also provides a channel for a user to provide feedback regarding the application. Multiple users may submit feedback messages each of which are enriched with contextual information related to the application at the time the message is submitted. Each feedback message is assigned to a category based on the content of the feedback message and contextual information of the notification. A heat map may be generated to visualize a number of feedback messages associated with one or more categories.

Abstract: Techniques are disclosed for a bi-directional notification service. The techniques disclosed herein notify a user of an application in real-time based on a context of the application. A given notification may require a particular context before the notification can be presented to the user. The notification service also provides a channel for a user to provide feedback regarding the application. Multiple users may submit feedback messages each of which are enriched with contextual information related to the application at the time the message is submitted. Each feedback message is assigned to a category based on the content of the feedback message and contextual information of the notification. A heat map may be generated to visualize a number of feedback messages associated with one or more categories.

Abstract: A testing device in communication with a disc player includes a storage device and a display device. The storage stores a start command, an end command, and a reference value range of each of several performance parameters of the disc player. The start command is sent to the disc player a predetermined numbers times to obtain performance readings as the disc player reads data. The value of each performance reading of the disc player obtained each time the start command is transmitted is compared with a range of values preset for several performance parameters and the display device shows information indicating whether or not the disc player is acceptable.

Abstract: A detection apparatus communicating with an peripheral device includes a determining module, a detecting module, a converting module, a comparing module, and a control module. The determining module controls the detecting module to transmit a corresponding testing program to the peripheral device while determining disc information is received from the peripheral device. The detecting module further controls the converting module to convert the feedback information into a parameter while detecting whether feedback information is received from the peripheral device. The comparing module compares the converted parameter and the standard parameter to generate a corresponding control signal for controlling the control module to generate different prompting information for indicating different detecting result of the peripheral device.

Abstract: A testing device for testing performance parameters of a disc player which includes a display, and a storage. The storage at least one sector table associated with a disc in the disc player, each sector table recording sector information corresponding to a plurality of physical sectors of the disc, a testing command associated with each physical sector, and a reference value range of each of performance parameters of the disc player. The testing command corresponding to the physical sector of the disk is obtained to be executed by the disc player to obtain a value of each performance parameter of the disc player. The testing device determines whether the disc player is qualified or not according to the obtained value.

Abstract: A testing device for testing performance parameters of a disc player includes a display, and a storage that records a plurality of types of different discs, a plurality of testing commands each corresponding to a type of discs, and a reference value range of each of performance parameters of the disc player. The testing command corresponding to the type of a disc is obtained to be executed by the disc player to obtain a value of each performance parameter of the disc player. The testing device determines whether the disc player is qualified or not according to the obtained value.

Abstract: The present invention is related to microelectronic technologies, and discloses specifically a dynamic random access memory (DRAM) array and methods of making the same. The DRAM array uses vertical MOS field effect transistors as array devices for the DRAM, and a buried metal silicide layer as buried bit lines for connecting multiple consecutive vertical MOS field effect transistor array devices. Each of the vertical MOS field-effect-transistor array devices includes a double gate structure with a buried layer of metal, which acts at the same time as buried word lines for the DRAM array. The DRAM array according to the present invention provides increased DRAM integration density, reduced buried bit line resistivity, and improved memory performance of the array devices. The present invention also provides a method of making a DRAM array.

Abstract: The present invention discloses a semiconductor memory device comprising a source, a drain, a floating gate, a control gate, a recess channel and a gated p-n diode. The said p-n diode connects said floating gate and said drain. The said floating gate is for charge storage purpose, it can be electrically charged or discharged by current flowing through the gated p-n diode. An array of memory cells formed by the disclosed semiconductor memory device is proposed. Furthermore, an operating method and a method for producing the disclosed semiconductor memory device and array are described.

Abstract: An integrated circuit includes a transistor of a first type with a first gate electrode and a transistor of a second type with a second gate electrode. The first gate electrode is formed in a first gate groove that is defined in a semiconductor substrate, and the second gate electrode is formed in a second gate groove defined in the semiconductor substrate. The first gate electrode completely fills a space between two adjacent first isolation trenches, and the second gate electrode partially fills a space between two adjacent second isolation trenches, with substrate portions being arranged between the second gate electrode and the adjacent second isolation trenches, respectively.

Abstract: A method of manufacturing a transistor is disclosed. The method includes forming a first and a second source/drain regions, a channel connecting the first and the second source/drain regions and a gate electrode for controlling the conductivity of the channel. The gate electrode is formed by defining a gate groove in the substrate, and defining a pocket in each of the isolation trenches at a position adjacent to the groove so that the two pockets will be connected with the groove and the groove is disposed between the two pockets. A gate insulating material is provided at an interface between the active area and the groove and at an interface between the active area and the pockets. A gate electrode material is deposited so as to fill the groove and the two pockets.

Abstract: An integrated circuit includes a plurality of memory cells, each memory cell including a memory element and a select device; and a plurality of word lines and bit lines connected to the memory cells. The bit lines, word lines, and the memory elements are arranged above the select devices.

Abstract: The present invention discloses a semiconductor memory device comprising a source, a drain, a floating gate, a control gate, a recess channel and a gated p-n diode. The said p-n diode connects said floating gate and said drain. The said floating gate is for charge storage purpose, it can be electrically charged or discharged by current flowing through the gated p-n diode. An array of memory cells formed by the disclosed semiconductor memory device is proposed. Furthermore, an operating method and a method for producing the disclosed semiconductor memory device and array are described.

Abstract: The present invention provides an integrated circuit with a floating body transistor comprising two source/drain regions and a floating body region arranged between the two source/drain regions comprising: a back gate electrode separated from the floating body by a first dielectric layer; a control gate electrode, separated from the floating body by a second dielectric layer and overlying the back gate electrode; and a third dielectric layer arranged between the back gate electrode and the control gate electrode. The present invention provides also a method of manufacturing an integrated circuit and a method of operating an integrated circuit.

Abstract: An integrated circuit having an array of memory cells is disclosed. One embodiment provides selection transistors for selecting one of a plurality of memory cells. The selection transistor is a tunnel field effect transistor in order to reduce a leakage current when the transistor is in its non-conducting state. Furthermore an operation method and a method for production are described.

Abstract: A method of manufacturing a transistor. In one embodiment, the method includes forming a gate electrode by defining a gate groove in the substrate. A plate-like portion is defined in each of the trenches at a position adjacent to the groove so that the two plate-like portions will be connected with the groove and the groove is disposed between two plate-like portions. In one embodiment, the two plate-like portions are defined by an etching process which selectively etches the isolating material of the isolation trenches with respect to the semiconductor substrate material. A gate insulating material is provided at an interface between the active area and the groove and the interface between the active area and the plate-like portions, and a gate electrode material is deposited so as to fill the groove and the two plate-like portions.

Abstract: This invention relates to an organic electroluminescence (EL) device and to the use of a tris-cyclometalated iridium complex with a 3-Phenyl-azine ligand for thin-film type organic electroluminescence devices.

Abstract: An integrated circuit includes a transistor of a first type with a first gate electrode and a transistor of a second type with a second gate electrode. The first gate electrode is formed in a first gate groove that is defined in a semiconductor substrate, and the second gate electrode is formed in a second gate groove defined in the semiconductor substrate. The first gate electrode completely fills a space between two adjacent first isolation trenches, and the second gate electrode partially fills a space between two adjacent second isolation trenches, with substrate portions being arranged between the second gate electrode and the adjacent second isolation trenches, respectively.

Abstract: A transistor which can in particular be used in memory cells of a Dynamic Random Access Memory a memory cell and a method of manufacturing a transistor is disclosed. In one embodiment the transistor is a dual-fin field effect transistor. The transistor includes a first and a second source/drain regions, a channel connecting the first and second source/drain regions, a gate electrode for controlling an electrical current flowing between the first and second source/drain regions. The gate electrode is insulated from the channel by a gate dielectric, wherein the gate electrode is disposed in a gate groove extending in the substrate surface so that the channel comprises two fin-like channel portions extending between the first and second source/drain regions in a cross-sectional view taken perpendicularly to a line connecting the first and the second source/drain regions, the gate electrode delimiting each of the fin-like channel portions at one side thereof.

Abstract: A compound of formula [I]: X—R[I] wherein X represents the group: and R is either (i) represented by the formula [II] wherein n is 1 or 2, and the or each R7 group is independently selected from the group consisting of hydrogen and halogen atoms, cyano, nitro, mercapto, carbonyl and sulfone groups, and optionally substituted alkyl, haloalkyl, hydroxyalkyl, aryl, alkoxy, aryloxy, alkylamino, arylamino, alkylthio, arylthio, ester, siloxy, cyclic hydrocarbon and heterocyclic groups; or (ii) is selected from the group consisting of optionally substituted alkyl, hydroxyalkyl, aryl, cyclic hydrocarbon and heterocyclic groups; wherein in each case R1–R6 are each independently selected from the group consisting of hydrogen and halogen atoms, cyano, nitro, mercapto, carbonyl and sulfone groups, and optionally substituted alkyl, haloalkyl, hydroxyalkyl, aryl, alkoxy, aryloxy, alkylamino, arylamino, alkylthio, arylthio, ester, siloxy, cyclic hydrocarbon and heterocyclic groups.