Abstract: A light emitting diode (LED) pixel array and method of fabrication thereof. A semiconductor wafer template includes a dielectric layer formed over a lower n-type gallium nitride (n-GaN) layer. A first aperture and a second aperture are formed through the dielectric layer and extending to the lower n-GaN layer, the second aperture being narrower than the first aperture. A mesa is formed within the first aperture by successively forming a mesa n-GaN layer, a mesa MQW layer above the mesa n-GaN layer, and a mesa p-GaN layer above the mesa MQW layer. A pyramid having sidewalls is formed within the second aperture by successively forming a pyramidal n-GaN layer, a pyramidal MQW layer, and a pyramidal p-GaN layer. The mesa n-GaN layer, mesa MQW layer, and mesa p-GaN layer form a mesa LED. The pyramidal n-GaN layer, pyramidal MQW layer, and pyramidal p-GaN layer form a pyramid LED.

Abstract: A light emitting diode (LED) pixel array and method of fabrication thereof. A semiconductor wafer template includes a successively stacked first n-GaN layer, first MQW layer, p-GaN layer, and dielectric layer. A plurality of apertures is formed through the dielectric layer, extending to the p-GaN layer. A plurality of mesas is formed by forming, within each aperture, a second MQW layer and a second n-GaN layer above each second MQW layer. The second n-GaN layer and second MQW layer of each mesa form a respective mesa LED with the p-GaN layer. The first n-GaN layer and first MQW layer form a lower LED with the p-GaN layer.

Abstract: A light emitting diode (LED) pixel array and method of fabrication thereof. A semiconductor wafer template includes a successively stacked lower n-GaN layer, lower MQW layer, lower p-GaN layer, upper n-GaN layer, and dielectric layer. A plurality of apertures is formed through the dielectric layer, extending to the upper n-GaN layer. A plurality of mesas is formed by forming, within each aperture, a mesa n-GaN layer, a mesa MQW layer above each mesa n-GaN layer, and a mesa p-GaN layer above each mesa MQW layer. The mesa n-GaN layer, mesa MQW layer, and mesa p-GaN layer of each mesa form a respective mesa LED. The lower n-GaN layer, lower MQW layer, and lower p-GaN layer form a lower LED.

Abstract: The present disclosure belongs to the technical field of microorganisms, and specifically relates to a non-toxin-producing Aspergillus flavus strain, a microbial inoculant, a preparation, and use. The present disclosure provides a non-toxin-producing Aspergillus flavus strain EXY1A109 with a deposit number of CCTCC No: M20221465. The strain can effectively inhibit the production of aflatoxin B1, aflatoxin B2, aflatoxin G1, and aflatoxin G2 by a toxin-producing Aspergillus flavus strain. The results of examples show that when an Aspergillus flavus strain EXY1A109 spore suspension and a strain CGMCC 3.4408 spore suspension are mixed in an equal volume, the Aspergillus flavus strain EXY1A109 spore suspension and the strain CGMCC 3.4408 spore suspension each have a concentration of 1×106, and the strain EXY1A109 has a toxin-producing inhibition rate of 99.71% against the strain CGMCC 3.4408. This Aspergillus flavus strain shows a desirable application effect.

Abstract: An anti-fuse unit structure includes a substrate, an anti-fuse device, and a select transistor. The anti-fuse device is formed in the substrate and comprises a first gate structure, a first source doped region, and a first drain doped region, wherein the first gate structure is electrically connected to the first drain doped region. The select transistor is formed in the substrate and matched with the anti-fuse device, and comprises a second gate structure, a second source doped region and a second drain doped region, wherein the second drain doped region is electrically connected to the first source doped region.

Abstract: In a described example, a method of forming a capacitor includes forming a doped polysilicon layer over a semiconductor substrate. The method also includes forming a dielectric layer on the doped polysilicon layer. The method also includes forming an undoped polysilicon layer on the dielectric layer.

Abstract: In a described example, a method of forming a capacitor includes forming a doped polysilicon layer over a semiconductor substrate. The method also includes forming a dielectric layer on the doped polysilicon layer. The method also includes forming an undoped polysilicon layer on the dielectric layer.

Abstract: A One Time Programmable (OTP) memory can have a memory cell, which includes two series diodes as a fuse structure.

Abstract: A device includes a light emitting diode (LED) configured to emit light characterized by a peak wavelength, a lower wavelength band extending across lower wavelengths than the peak wavelength, and a higher wavelength band extending across higher wavelengths than the peak wavelength. The device also includes a reflector positioned in a first direction from the LED. The device also includes a distributed Bragg reflector (DBR) having a lower reflectance than the reflector, positioned in a second direction from the LED opposite the first direction, and configured to block light within a stopband overlapping a portion of the lower wavelength band or a portion of the higher wavelength band but not overlapping the peak wavelength, such that the DBR propagates filtered light in the second direction.

Abstract: A method of fabricating a semiconductor device includes forming, above a substrate surface, a plurality of distributed Bragg reflector (DBR) layers to form a DBR; forming, above the DBR, a first light emitting diode (LED) configured to emit light; and forming, above the first LED, a first reflector having a higher reflectance than the DBR, such that the first reflector and the DBR define a first resonant cavity having a length effective to collimate a first wavelength of the light emitted by the first LED and propagate the collimated light of the first wavelength through the DBR.

Abstract: A method of fabricating a semiconductor device having a distributed Bragg reflector (DBR) includes depositing, above a DBR deposition surface, a plurality of DBR layers to form a DBR, forming at least one aperture extending through the plurality of DBR layers to expose each DBR layer, and applying electrochemical etching to the plurality of DBR layers via the at least one aperture, thereby transforming at least one DBR layer of the plurality of DBR layers into a nanoporous structure.

Abstract: Embodiments of this application relate to a data processing method and a terminal. The method includes: obtaining a first network wakeup parameter, where the first network wakeup parameter is used to wake up an application program; performing reconfiguration processing on the first network wakeup parameter based on a preset first configuration condition to obtain a second network wakeup parameter; and configuring a driver of the terminal based on the second network wakeup parameter. The second network wakeup parameter is written into Wi-Fi firmware, so that the Wi-Fi firmware directly performs processing without waking up the application program when the first network wakeup parameter is received next time. Therefore, power consumption of the terminal is reduced, and a standby time of the terminal is prolonged.

Abstract: A semiconductor device testing system, with a platform for supporting a semiconductor substrate, a light emitting system directed toward the platform, a controller, coupled to the light emitting system and adapted to selectively alter an operational parameter of the light emitting system, and a tester configured to characterize an electrical parameter of an electrical device formed in or over the semiconductor substrate while the electrical device is illuminated by one or more wavelengths of light emitted by the light emitting system under direction of the controller.

Abstract: A method of fabricating an integrated circuit includes etching trenches in a first surface of a semiconductor layer. A trench dielectric layer is formed over the first surface and over bottoms and sidewalls of the trenches and a doped polysilicon layer is formed over the trench dielectric layer and within the trenches. The doped polysilicon layer is patterned to form a polysilicon bridge that connects to the polysilicon within the filled trenches and a blanket implant of a first dopant is directed to the polysilicon bridge and to the first surface. The blanket implant forms a contact region extending from the first surface into the semiconductor layer.

Abstract: A method of fabricating an integrated circuit includes etching trenches in a first surface of a semiconductor layer. A trench dielectric layer is formed over the first surface and over bottoms and sidewalls of the trenches and a doped polysilicon layer is formed over the trench dielectric layer and within the trenches. The doped polysilicon layer is patterned to form a polysilicon bridge that connects to the polysilicon within the filled trenches and a blanket implant of a first dopant is directed to the polysilicon bridge and to the first surface. The blanket implant forms a contact region extending from the first surface into the semiconductor layer.

Abstract: A connection analysis method for a multi-port nested model and a medium. The method includes: acquiring instance information and nested relationships of a multi-port nested model, and building an instance relationship tree; reading port information and connection information of instances, and adding the port information and the connection information to the instance relationship tree; acquiring the port information and the connection information of the instances of each node layer by layer according to the instance relationship tree to build a connection dictionary; and acquiring port-to-port connection information of the instances by retrieving the connection dictionary to perform connection analysis on the multi-port nested model.

Abstract: A simultaneous phase-shift point diffraction interferometer and method for detecting wave aberration. The interferometer comprises an ideal spherical wave generation module, an optical system to be measured, an image plane mask, a polarization phase shift module, a two-dimensional polarization imaging photodetector and a data processing unit. Single photodetector is adopted to realize simultaneous detection of more than three phase shift interference patterns, and has the advantages that environmental interference suppression, a flexible optical path, high measurement accuracy, and calibration of system errors of the interferometer may be realized.

Abstract: Embodiments of this application relate to a data processing method and a terminal. The method includes: obtaining a first network wakeup parameter, where the first network wakeup parameter is used to wake up an application program; performing reconfiguration processing on the first network wakeup parameter based on a preset first configuration condition to obtain a second network wakeup parameter; and configuring a driver of the terminal based on the second network wakeup parameter. The second network wakeup parameter is written into Wi-Fi firmware, so that the Wi-Fi firmware directly performs processing without waking up the application program when the first network wakeup parameter is received next time. Therefore, power consumption of the terminal is reduced, and a standby time of the terminal is prolonged.

Abstract: A connection analysis method for a multi-port nested model and a medium. The method includes: acquiring instance information and nested relationships of a multi-port nested model, and building an instance relationship tree; reading port information and connection information of instances, and adding the port information and the connection information to the instance relationship tree; acquiring the port information and the connection information of the instances of each node layer by layer according to the instance relationship tree to build a connection dictionary; and acquiring port-to-port connection information of the instances by retrieving the connection dictionary to perform connection analysis on the multi-port nested model.

Abstract: A simultaneous phase-shift point diffraction interferometer and method for detecting wave aberration. The interferometer comprises an ideal spherical wave generation module, an optical system to be measured, an image plane mask, a polarization phase shift module, a two-dimensional polarization imaging photodetector and a data processing unit. Single photodetector is adopted to realize simultaneous detection of more than three phase shift interference patterns, and has the advantages that environmental interference suppression, a flexible optical path, high measurement accuracy, and calibration of system errors of the interferometer may be realized.