Abstract: According to some example embodiments of the present disclosure, in a method for a memory lookup mechanism in a high-bandwidth memory system, the method includes: using a memory die to conduct a multiplication operation using a lookup table (LUT) methodology by accessing a LUT, which includes floating point operation results, stored on the memory die; sending, by the memory die, a result of the multiplication operation to a logic die including a processor and a buffer; and conducting, by the logic die, a matrix multiplication operation using computation units.

Abstract: Disclosed are a pyrrolidine compound as represented by formula (I) or a pharmaceutically acceptable salt thereof, a pharmaceutical composition containing same, and the use of the pharmaceutical composition as a selective estrogen receptor degrader (SERD) in the prevention or treatment of estrogen receptor-related diseases.

Abstract: According to some example embodiments of the present disclosure, in a method for a memory lookup mechanism in a high-bandwidth memory system, the method includes: using a memory die to conduct a multiplication operation using a lookup table (LUT) methodology by accessing a LUT, which includes floating point operation results, stored on the memory die; sending, by the memory die, a result of the multiplication operation to a logic die including a processor and a buffer; and conducting, by the logic die, a matrix multiplication operation using computation units.

Abstract: A storage device and method of controlling a storage device are disclosed. The storage device includes a host, a logic die, and a high bandwidth memory stack including a memory die. A computation lookup table is stored on a memory array of the memory die. The host sends a command to perform an operation utilizing a kernel and a plurality of input feature maps, includes finding the product of a weight of the kernel and values of multiple input feature maps. The computation lookup table includes a row corresponding to a weight of the kernel, and a column corresponding to a value of the input feature maps. A result value stored at a position corresponding to a row and a column is the product of the weight corresponding to the row and the value corresponding to the column.

Abstract: A storage device and method of controlling a storage device are disclosed. The storage device includes a host, a logic die, and a high bandwidth memory stack including a memory die. A computation lookup table is stored on a memory array of the memory die. The host sends a command to perform an operation utilizing a kernel and a plurality of input feature maps, includes finding the product of a weight of the kernel and values of multiple input feature maps. The computation lookup table includes a row corresponding to a weight of the kernel, and a column corresponding to a value of the input feature maps. A result value stored at a position corresponding to a row and a column is the product of the weight corresponding to the row and the value corresponding to the column.

Abstract: The present application describes a substituted aryl compound used as an RAD51 inhibitor and a pharmaceutically acceptable salt thereof. The compound has the structure as represented by Formula (I) and has the substituents and structural features as described in the present application. Furthermore, the present application describes a pharmaceutical composition containing the compound as represented by Formula (I) or the pharmaceutically acceptable salt thereof, and the use of the compound as represented by Formula (I) or the pharmaceutically acceptable salt thereof and the pharmaceutical composition containing same in the preparation of a drug for preventing or treating RAD51 mediated diseases.

Abstract: According to some example embodiments of the present disclosure, in a method for a memory lookup mechanism in a high-bandwidth memory system, the method includes: using a memory die to conduct a multiplication operation using a lookup table (LUT) methodology by accessing a LUT, which includes floating point operation results, stored on the memory die; sending, by the memory die, a result of the multiplication operation to a logic die including a processor and a buffer; and conducting, by the logic die, a matrix multiplication operation using computation units.

Abstract: According to one general aspect, an apparatus may include a memory circuit die configured to store a lookup table that converts first data to second data. The apparatus may also include a logic circuit die comprising combinatorial logic circuits configured to receive the second data. The apparatus may further include an optical via coupled between the memory circuit die and the logical circuit die and configured to transfer second data between the memory circuit die and the logic circuit die.

Abstract: According to one general aspect, an apparatus may include a memory circuit die configured to store a lookup table that converts first data to second data. The apparatus may also include a logic circuit die comprising combinatorial logic circuits configured to receive the second data. The apparatus may further include an optical via coupled between the memory circuit die and the logical circuit die and configured to transfer second data between the memory circuit die and the logic circuit die.

Abstract: According to some example embodiments of the present disclosure, in a method for a memory lookup mechanism in a high-bandwidth memory system, the method includes: using a memory die to conduct a multiplication operation using a lookup table (LUT) methodology by accessing a LUT, which includes floating point operation results, stored on the memory die; sending, by the memory die, a result of the multiplication operation to a logic die including a processor and a buffer; and conducting, by the logic die, a matrix multiplication operation using computation units.

Abstract: A computing accelerator using a lookup table. The accelerator may accelerate floating point multiplications by retrieving the fraction portion of the product of two floating-point operands from a lookup table, or by retrieving the product of two floating-point operands of two floating-point operands from a lookup table, or it may retrieve dot products of floating point vectors from a lookup table. The accelerator may be implemented in a three-dimensional memory assembly. It may use approximation, the symmetry of a multiplication lookup table, and zero-skipping to improve performance.

Abstract: The present disclosure provides a method for preparing a doped YAG single crystal fiber. The method may include preparing a doped YAG crystal rod; preparing a doped YAG single crystal fiber core by immersing at least a portion of the doped YAG crystal rod in an acid solution; performing a cylindrical surface polishing operation on the doped YAG single crystal fiber core by causing a stirrer to rotate to drive a polishing liquid to rotate; placing the doped YAG single crystal fiber core into a growth zone of a growth chamber and placing a raw material into a dissolution zone of the growth chamber; heating the growth zone and the dissolution zone by a two-stage heating device, respectively; and preparing a doped YAG single crystal fiber by growing a YAG single crystal fiber cladding on a surface of the doped YAG single crystal fiber core.

Abstract: A high bandwidth memory (HBM) system includes a first HBM+ card. The first HBM+ card includes a plurality of HBM+ cubes. Each HBM+ cube has a logic die and a memory die. The first HBM+ card also includes a HBM+ card controller coupled to each of the plurality of HBM+ cubes and configured to interface with a host, a pin connection configured to connect to the host, and a fabric connection configured to connect to at least one HBM+ card.

Abstract: A storage device and method of controlling a storage device are disclosed. The storage device includes a host, a logic die, and a high bandwidth memory stack including a memory die. A computation lookup table is stored on a memory array of the memory die. The host sends a command to perform an operation utilizing a kernel and a plurality of input feature maps, includes finding the product of a weight of the kernel and values of multiple input feature maps. The computation lookup table includes a row corresponding to a weight of the kernel, and a column corresponding to a value of the input feature maps. A result value stored at a position corresponding to a row and a column is the product of the weight corresponding to the row and the value corresponding to the column.

Abstract: A general matrix-matrix multiplication (GEMM) dataflow accelerator circuit is disclosed that includes a smart 3D stacking DRAM architecture. The accelerator circuit includes a memory bank, a peripheral lookup table stored in the memory bank, and a first vector buffer to store a first vector that is used as a row address into the lookup table. The circuit includes a second vector buffer to store a second vector that is used as a column address into the lookup table, and lookup table buffers to receive and store lookup table entries from the lookup table. The circuit further includes adders to sum the first product and a second product, and an output buffer to store the sum. The lookup table buffers determine a product of the first vector and the second vector without performing a multiply operation. The embodiments include a hierarchical lookup architecture to reduce latency. Accumulation results are propagated in a systolic manner.

Abstract: According to some example embodiments of the present disclosure, in a method for a memory lookup mechanism in a high-bandwidth memory system, the method includes: using a memory die to conduct a multiplication operation using a lookup table (LUT) methodology by accessing a LUT, which includes floating point operation results, stored on the memory die; sending, by the memory die, a result of the multiplication operation to a logic die including a processor and a buffer; and conducting, by the logic die, a matrix multiplication operation using computation units.

Abstract: The invention discloses a method and a device for treating cyanobacteria in a water area based on the principle of biological competition, the method comprising: finding an area where cyanobacteria most easily accumulate, i.e. a concave bank of a water area, and setting up an algae interception net around the area; quickly and largely clearing the cyanobacteria in the area by means of manual or mechanical catching; planting emerged plants on the shoreline of the water area to fundamentally improve water quality; and additionally, densely arranging treatment tanks in a larger water area to kill the cyanobacteria gradually, and collecting dead cyanobacteria to prevent them from polluting the water area subsequently; and collecting and treating the tanks regularly for recycling.

Abstract: A high bandwidth memory (HBM) system includes a first HBM+ card. The first HBM+ card includes a plurality of HBM+ cubes. Each HBM+ cube has a logic die and a memory die. The first HBM+ card also includes a HBM+ card controller coupled to each of the plurality of HBM+ cubes and configured to interface with a host, a pin connection configured to connect to the host, and a fabric connection configured to connect to at least one HBM+ card.

Abstract: The present disclosure provides a method for preparing a doped YAG single crystal fiber. The method may include placing a doped YAG single crystal fiber core into a growth zone and placing a raw material into a dissolution zone; adding a mineralizer into the growth chamber to cause the mineralizer to immerse the raw material and the doped YAG single crystal fiber core; heating the growth zone and the dissolution zone by a two-stage heating device, respectively; and preparing a doped YAG single crystal fiber by growing a YAG single crystal fiber cladding on a surface of the doped YAG single crystal fiber core based on the doped YAG single crystal fiber core and the raw material under a preset pressure.

Abstract: A face capturing method and a related apparatus that are applicable to an electronic apparatus. The method includes: analyzing a captured first video stream to obtain a plurality of images (101); determining a first pattern including a plurality of first codes (102); buffering images of first frame numbers, corresponding to the first codes indicating images to be buffered, to buffers in sequence (103); when buffering the images, determining a second pattern including a plurality of second codes (104); buffering images of second frame numbers, corresponding to the second codes indicating images to be buffered, to the buffers in sequence (105); and when buffering the images, processing the images in the buffers in sequence on the basis of a face capturing algorithm and according to an order of the first numbers of the buffers, to obtain face images, and outputting the face images (106). The method prevents wastage of buffer resources.