Patents by Inventor Peng Jing

Peng Jing has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12056393
    Abstract: A method for exchanging messages is performed by a slave device, and includes: receiving a submission queue (SQ) tail doorbell from a host to learn that X SQ entries need to be processed, wherein “X” doesn't exceed a host SQ entry upper limit; performing multiple read operations according to the SQ tail doorbell to read the X SQ entries from the host, wherein the slave device reads Y SQ entries at most in each read operation, and “Y” is smaller than “X” and doesn't exceed a slave device SQ entry upper limit; preparing P completion queue (CQ) entries; performing multiple write operations to transmit the P CQ entries to the host, wherein the slave device transmits Q CQ entries at most in each write operation, and “Q” is smaller than “P” and doesn't exceed a slave device CQ entry upper limit; and transmitting a CQ tail doorbell to the host.
    Type: Grant
    Filed: July 21, 2021
    Date of Patent: August 6, 2024
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Shi-Yao Zhao, Dao-Fu Wang, Yong-Peng Jing
  • Publication number: 20240241837
    Abstract: A data encryption and decryption system and a data encryption and decryption method for the same are provided. The system includes a memory controlling circuit and an encryption and decryption circuit. In write operation, the encryption and decryption circuit executes an encryption algorithm on write address to obtain first seed data, executes a first scrambling process on initial write data to generate first scrambled data, and executes a second scrambling process on the first scrambled data according to common seed data, so as to generate encrypted write data. The memory controlling circuit writes the encrypted write data into a memory unit according to the write address.
    Type: Application
    Filed: July 26, 2023
    Publication date: July 18, 2024
    Inventors: YU ZHANG, YONG-PENG JING
  • Patent number: 11669445
    Abstract: A method performed by a slave device to obtain a host memory address includes: inquiring a description list to obtain information of an allocated memory of a host; dividing the allocated memory into N storage spaces according to the information; using a first memory space of the N storage spaces to store a first level look-up table indicating physical addresses of the N storage spaces; dividing the first memory space into M storage spaces; storing a second level look-up table in the slave device to indicate physical addresses of the M storage spaces; inquiring the second level look-up table according to a logical address and obtaining a first index indicating a physical address of one of the M storage spaces; and inquiring the first level look-up table according to the first index and obtaining a second index indicating a physical address of one of the N storage spaces.
    Type: Grant
    Filed: July 20, 2021
    Date of Patent: June 6, 2023
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Shi-Yao Zhao, Dao-Fu Wang, Yong-Peng Jing
  • Publication number: 20230132621
    Abstract: 1,5-dihydro-2,4-benzodiazepine-3-one derivatives, such as a compound represented by formula I, acts on 5-HT2A and 5-HT2C receptors. The selectivity for 5-HT2A is superior or similar to pimavanserin. The derivative is used for treating schizophrenia or Parkinson’s disease, dementia-related behavioral disorders, and psychosis. The antipsychotic activity of the compound is equivalent to that of pimavanserin, the side effects of sedation and and worsening of exercise are less than those of pimavanserin, and cardiotoxicity is less than that of pimavanserin.
    Type: Application
    Filed: October 20, 2022
    Publication date: May 4, 2023
    Inventors: Xiangqing XU, Yinli QIU, Qiang GUO, Minquan YU, Song ZHAO, Quxiang LI, Peng JING, Yuanyuan HOU, Yingying DONG, Guosheng WU, Shuang ZHANG, Aijun LU
  • Patent number: 11606095
    Abstract: Disclosed is a reference clock gating circuit for outputting a reliable reference clock according to an external clock. The circuit includes a detection circuit and a gating component. The detection circuit includes: a first counter counting according to triggers of the external clock and thereby generating a first clock number; a second counter counting according to triggers of an accurate slow clock and thereby generating a second clock number; and a decision circuit determining whether a ratio of the first clock number to the second clock number satisfies a predetermined condition after the second clock number reaches a predetermined number, and thereby generating a gating signal to control the gating component. If the ratio satisfies the predetermined condition, the gating component receives the external clock and outputs it as the reference clock; and if the ratio doesn't satisfy the predetermined condition, the gating component doesn't output the external clock.
    Type: Grant
    Filed: July 20, 2021
    Date of Patent: March 14, 2023
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Shi-Yao Zhao, Dao-Fu Wang, Yong-Peng Jing
  • Publication number: 20220156006
    Abstract: A method for exchanging messages is performed by a slave device, and includes: receiving a submission queue (SQ) tail doorbell from a host to learn that X SQ entries need to be processed, wherein “X” doesn't exceed a host SQ entry upper limit; performing multiple read operations according to the SQ tail doorbell to read the X SQ entries from the host, wherein the slave device reads Y SQ entries at most in each read operation, and “Y” is smaller than “X” and doesn't exceed a slave device SQ entry upper limit; preparing P completion queue (CQ) entries; performing multiple write operations to transmit the P CQ entries to the host, wherein the slave device transmits Q CQ entries at most in each write operation, and “Q” is smaller than “P” and doesn't exceed a slave device CQ entry upper limit; and transmitting a CQ tail doorbell to the host.
    Type: Application
    Filed: July 21, 2021
    Publication date: May 19, 2022
    Inventors: SHI-YAO ZHAO, DAO-FU WANG, YONG-PENG JING
  • Publication number: 20220158642
    Abstract: Disclosed is a reference clock gating circuit for outputting a reliable reference clock according to an external clock. The circuit includes a detection circuit and a gating component. The detection circuit includes: a first counter counting according to triggers of the external clock and thereby generating a first clock number; a second counter counting according to triggers of an accurate slow clock and thereby generating a second clock number; and a decision circuit determining whether a ratio of the first clock number to the second clock number satisfies a predetermined condition after the second clock number reaches a predetermined number, and thereby generating a gating signal to control the gating component. If the ratio satisfies the predetermined condition, the gating component receives the external clock and outputs it as the reference clock; and if the ratio doesn't satisfy the predetermined condition, the gating component doesn't output the external clock.
    Type: Application
    Filed: July 20, 2021
    Publication date: May 19, 2022
    Inventors: SHI-YAO ZHAO, DAO-FU WANG, YONG-PENG JING
  • Publication number: 20220147449
    Abstract: A method performed by a slave device to obtain a host memory address includes: inquiring a description list to obtain information of an allocated memory of a host; dividing the allocated memory into N storage spaces according to the information; using a first memory space of the N storage spaces to store a first level look-up table indicating physical addresses of the N storage spaces; dividing the first memory space into M storage spaces; storing a second level look-up table in the slave device to indicate physical addresses of the M storage spaces; inquiring the second level look-up table according to a logical address and obtaining a first index indicating a physical address of one of the M storage spaces; and inquiring the first level look-up table according to the first index and obtaining a second index indicating a physical address of one of the N storage spaces.
    Type: Application
    Filed: July 20, 2021
    Publication date: May 12, 2022
    Inventors: SHI-YAO ZHAO, DAO-FU WANG, YONG-PENG JING
  • Publication number: 20220048887
    Abstract: An impurity A, an impurity B and an impurity G and preparation methods therefor, and an application as a reference standard for quality control of a compound as represented by formula VI are described.
    Type: Application
    Filed: December 16, 2019
    Publication date: February 17, 2022
    Inventors: Fei DOU, Peng JING
  • Patent number: 10859561
    Abstract: The invention discloses a proteoliposome or a planar lipid bilayer membrane comprising a single protein manufactured using glycerol or polyethylene glycols (PEG) in the rehydration step. Products so prepared are useful for nanopore sensing technology, including ultrafast DNA sequencing and biomedical diagnostic applications.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: December 8, 2020
    Assignee: Purdue Research Foundation
    Inventor: Peng Jing
  • Publication number: 20190017990
    Abstract: The invention discloses a proteoliposome or a planar lipid bilayer membrane comprising a single protein manufactured using glycerol or polyethylene glycols (PEG) in the rehydration step. Products so prepared are useful for nanopore sensing technology, including ultrafast DNA sequencing and biomedical diagnostic applications.
    Type: Application
    Filed: September 20, 2018
    Publication date: January 17, 2019
    Applicant: Purdue Research Foundation
    Inventor: Peng Jing
  • Patent number: 10107791
    Abstract: The invention discloses a method to prepare proteoliposomes using glycerol or polyethylene glycols (PEG) in the rehydration step. The method eliminates the use of expensive surfactants and subsequent time-consuming removal of those surfactants during the preparation of proteoliposomes. The fusible proteoliposome reconstituted with phage portal proteins or other hydrophobic channel proteins are useful for nanopore sensing technology, including ultrafast DNA sequencing and biomedical diagnostic applications.
    Type: Grant
    Filed: January 5, 2017
    Date of Patent: October 23, 2018
    Assignee: PURDUE RESEARCH FOUNDATION
    Inventor: Peng Jing
  • Publication number: 20170190798
    Abstract: The invention discloses a method to prepare proteoliposomes using glycerol or polyethylene glycols (PEG) in the rehydration step. The method eliminates the use of expensive surfactants and subsequent time-consuming removal of those surfactants during the preparation of proteoliposomes. The fusible proteoliposome reconstituted with phage portal proteins or other hydrophobic channel proteins are useful for nanopore sensing technology, including ultrafast DNA sequencing and biomedical diagnostic applications.
    Type: Application
    Filed: January 5, 2017
    Publication date: July 6, 2017
    Inventor: Peng Jing
  • Publication number: 20100058085
    Abstract: A power-saving device and method are applicable to a first electronic device having at least one connection interface, and the first electronic device is coupled to a second electronic device via a bus. The power-saving device includes a detection circuit, a power control circuit, and a connection control circuit. The detection circuit is coupled to the connection interface, to detect a load state of the connection interface and generate a detection signal. The power control circuit controls power supplied to the first electronic device via the bus in response to a state of the detection signal. The connection control circuit controls a connection state of the bus according to the detection signal.
    Type: Application
    Filed: August 17, 2009
    Publication date: March 4, 2010
    Applicant: REALTEK SEMICONDUCTOR CORP.
    Inventors: Chih-Ching Chien, Ying-Hui Zhu, Wen-Bin Wu, Yong-Peng Jing
  • Patent number: 7309253
    Abstract: A battery cover fixing mechanism is provided for coupling a cover (1) to a housing (2) of a portable electronic device. The battery cover fixing mechanism includes a blocking mechanism, an opening (16), a latching mechanism, a slot (20) and a cutout (24). The cover forms the blocking mechanism and defines the opening. The housing defines the slot and the cutout. The latching mechanism includes a block (30), an elastic member (32), a slider (34) having a blocking part, and a holder (36) fixed to the housing. The slider is slidably attached on the holder. The block is fixed on the slider and extends through the cutout and the opening. The blocking mechanism of the cover engages in the slot of the housing and with the blocking part of the slider. Two ends of the elastic member are respectively attached to the holder and the slider.
    Type: Grant
    Filed: November 2, 2005
    Date of Patent: December 18, 2007
    Assignees: Shenzhen Futaihong Precision Industrial Co., Ltd., Sutech Trading Limited
    Inventors: Peng-Jing Ge, Xing-Huang Luo, Rui-Hao Chen, Ye Liu, Shui-Yuan Qin, Hsiao-Hua Tu