Patents by Inventor Peng Li

Peng Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200017500
    Abstract: The disclosure provides new, stable, pharmaceutically acceptable co-crystal forms of 1-(4-fluoro-phenyl)-4-((6bR, 10aS)-3-methyl-2,3,6b,9, 10, 10a-hexahydro-1H,7H-pyrido[3?,4?:4,5]pyrrolo[1,2,3-de[quinoxalin-8-yl)-butan-1-one, together with methods of making and using them, and pharmaceutical compositions comprising them.
    Type: Application
    Filed: March 28, 2017
    Publication date: January 16, 2020
    Applicant: INTRA-CELLULAR THERAPIES, INC.
    Inventors: Peng LI, Edwin ARET
  • Publication number: 20200020044
    Abstract: A method, system, and computer program storage product determine determining a trajectory information type of a receipt submitted by an employee. Trajectory information associated with the receipt submitted by the employee is retrieved based on the trajectory information type. Trajectory information corresponding to a device associated with the employee is also retrieved. The receipt is determined as a valid receipt in response to the trajectory information associated with the receipt submitted by the employee matching the trajectory information associated with the device associated with the employee.
    Type: Application
    Filed: September 24, 2019
    Publication date: January 16, 2020
    Applicant: International Business Machines Corporation
    Inventors: Stephen CHU, Min GONG, Dong Sheng LI, Jun Chi YAN, Wei Peng ZHANG
  • Patent number: 10534658
    Abstract: Managing real-time monitoring alerts is provided. An alert is generated for one or more metrics exceeding corresponding defined metric threshold values. A root cause dependency table showing relationships between alerts is retrieved. It is determined whether current real-time metrics are needed from one or more monitoring agents that correspond to dependent alerts not triggered in an alert chain of the generated alert based on information in the root cause dependency table. In response to determining that the current real-time metrics are needed from the one or more monitoring agents that correspond to the dependent alerts not triggered in the alert chain of the generated alert based on the information in the root cause dependency table, the current real-time metrics are requested from the one or more monitoring agents that correspond to the dependent alerts not triggered in the alert chain.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: January 14, 2020
    Assignee: International Business Machines Corporation
    Inventors: Jin Shan Li, Rui Liu, Peng Peng Wang, Yang Yang
  • Patent number: 10533247
    Abstract: A method for growing carbon nanotubes is provided. A reactor including a reactor chamber and a substrate located in the reactor chamber is provide. The substrate is a hollow structure including a sidewall and a bottom. The hollow structure also defines an opening. The sidewall includes a carbon nanotube layer and catalyst particles dispersed in the carbon nanotube layer. A mixture of carbon source gas and carrier gas is introduced into the reactor chamber so that the mixture of carbon source gas and carrier gas flows into the hollow structure from the opening and out of the hollow structure through the sidewall. The hollow structure is heated.
    Type: Grant
    Filed: November 13, 2016
    Date of Patent: January 14, 2020
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yang Wu, Peng Liu, Yang Wei, Jia-Ping Wang, Kai-Li Jiang, Shou-Shan Fan
  • Patent number: 10535755
    Abstract: A method of forming a semiconductor device and resulting structures having closely packed vertical transistors with reduced contact resistance by forming a semiconductor structure on a doped region of a substrate, the semiconductor structure including a gate formed over a channel region of a semiconductor fin. A liner is formed on the gate and the semiconductor fin, and a dielectric layer is formed on the liner. Portions of the liner are removed to expose a top surface and sidewalls of the semiconductor fin and a sidewall of the dielectric layer. A recessed opening is formed by recessing portions of the liner from the exposed sidewall of the dielectric layer. A top epitaxy region is formed on the exposed portions of the semiconductor fin and dielectric layer such that an extension of the top epitaxy region fills the recessed opening. The top epitaxy region is confined between portions of the liner.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: January 14, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Zhenxing Bi, Kangguo Cheng, Juntao Li, Peng Xu
  • Patent number: 10535754
    Abstract: A method for manufacturing a semiconductor device includes forming a first semiconductor layer on a semiconductor substrate, forming a second semiconductor layer including a first concentration of germanium on the first semiconductor layer, and forming a third semiconductor layer on the second semiconductor layer. The first and third semiconductor layers each have a concentration of germanium, which is greater than the first concentration of germanium. The first, second and third semiconductor layers are patterned into at least one fin. The method further includes covering the second semiconductor layer with a mask layer. In the method, a bottom source/drain region and a top source/drain region are simultaneously grown from the first semiconductor layer and the third semiconductor layer, respectively. The mask layer is removed from the second semiconductor layer, and a gate structure is formed on and around the second semiconductor layer.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: January 14, 2020
    Assignee: International Business Machines Corporation
    Inventors: Peng Xu, ChoongHyun Lee, Kangguo Cheng, Juntao Li
  • Patent number: 10535733
    Abstract: A sacrificial gate stack for forming a nanosheet transistor includes a substrate. first, second and third silicon channel nanosheets formed over the substrate, and a first sandwich of germanium (Ge) containing layers disposed between the substrate and first silicon channel nanosheet. The stack also includes a second sandwich of Ge containing layers disposed between the first silicon channel nanosheet and the second silicon channel nanosheet; and a third sandwich of Ge containing layers disposed between the second silicon channel nanosheet and the third silicon channel nanosheet. Each sandwich includes first and second low Ge containing layers surrounding a silicon germanium (SiGe) sacrificial nanosheet that has a higher Ge concentration than the first and second low Ge containing layers.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: January 14, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Choonghyun Lee, Juntao Li, Peng Xu
  • Patent number: 10536430
    Abstract: A request message requesting a service is received from a terminal device. Computer code is transmitted to the terminal device, and a communication connection request is received from the terminal device in response to running the computer code on the terminal device. In response to receiving the communication connection request, a communication connection is established to the terminal device. A first IP address associated with the terminal device is determined based on one or more communications transmitted through the communication connection.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: January 14, 2020
    Assignee: Alibaba Group Holding Limited
    Inventors: Jianye Liu, Peng Zheng, Caiwei Li
  • Publication number: 20200012511
    Abstract: A method for operating an electronic device, the method including spawning a name space tool (NST) as part of a boot process of a host OS, wherein the NST is a process with a plurality of root privileges of the host OS. The method further includes spawning, by the NST, a container for a guest OS, wherein the container for the guest OS is mapped to a dedicated domain in the host OS, and dropping, by the NST, a root privilege of the host OS in response to spawning the container for the guest OS.
    Type: Application
    Filed: July 5, 2019
    Publication date: January 9, 2020
    Inventors: Guruprasad Ganesh, Sudhi Herle, Ahmed M. Azab, Rohan Bhutkar, Ivan Getta, Xun Chen, Wenbo Shen, Ruowen Wang, Haining Chen, Khaled Elwazeer, Mengmeng Li, Peng Ning, Hyungseok Yu, Myungsu Cha, Kyungsun Lee, Se Young Choi, Yurak Choe, Yong Shin, Kyoung-Joong Shin, Donguk Seo, Junyong Choi
  • Publication number: 20200014775
    Abstract: A method, system and computer-readable storage medium for grouping users of an online social network application are provided. The method includes: acquiring friend relation data of a first user, the friend relation data comprising one or more friend nodes; determining a weight of each of the friend nodes based on the friend relation data acquired; forming a first friend circle with a first friend node having a greatest weight among the friend nodes; traversing the friend nodes to find an optimum friend of the first friend circle; adding the optimum friend into the first friend circle; and repeating the traversing and adding until all optimum friends of the first friend circle are added into the first friend circle. The method determines the weight of each friend node based on the friend relation data and performs grouping by the weights, which is able to conduct as mart grouping with high speed, low throughput, and high efficiency.
    Type: Application
    Filed: September 17, 2019
    Publication date: January 9, 2020
    Inventors: Yuewen LIU, Chuan Chen, Peng He, Junming Mai, Yuhuang Li, Weihua Chen
  • Publication number: 20200013681
    Abstract: A method for manufacturing a vertical transistor device includes respectively forming a first and second plurality of fins in first and second device regions on a substrate. A plurality of bottom source/drain regions are formed adjacent lower portions of each of the fins, and a sacrificial layer is formed in the first device region on a first bottom source/drain region of the plurality of bottom source/drain regions. In the method, gate structures are formed on the bottom source/drain regions and sacrificial layer, and portions of the gate structures are removed to expose the sacrificial layer in the first device region and a second bottom source/drain region of the plurality of bottom source/drain regions in the second device region. The method further includes depositing a germanium oxide layer on the exposed sacrificial layer and second bottom source/drain region, and converting the germanium oxide layer to a plurality of silicide/germanide layers.
    Type: Application
    Filed: September 19, 2019
    Publication date: January 9, 2020
    Inventors: ChoongHyun Lee, Kangguo Cheng, Juntao Li, Peng Xu
  • Publication number: 20200010795
    Abstract: Provided herein are engineered cells, comprising: a chemical or biological moiety covalently bound to a cell surface glycan, wherein the chemical or biological moiety is selected from the group consisting of small molecule, polynucleotide, polypeptide, and antibody. Also provided are compositions comprising these engineered cells and methods of making and using the same.
    Type: Application
    Filed: February 1, 2018
    Publication date: January 9, 2020
    Inventors: Peng Wu, Jie Li, Yiran Zhou, Mingkuan Chen
  • Patent number: 10530614
    Abstract: Systems and methods for electronic devices including two or more semiconductor devices coupled via an interconnect. The interconnect includes multiple lanes each having a link between the first and second semiconductor devices. One or more lanes of the multiple lanes each include clock and data recovery circuitry to perform full clock and data recovery. One or more other lanes of the multiple lanes each do not include clock and data recovery circuitry and instead includes a phase adjustment and clock multiplier circuit that is slave to clock and data recovery circuitry of the one or more lanes.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: January 7, 2020
    Assignee: Intel Corporation
    Inventors: Hsinho Wu, Masashi Shimanouchi, Peng Li
  • Patent number: 10528463
    Abstract: Technologies for combining logical-to-physical address updates include a data storage device. The data storage device includes a non-volatile memory to store data and a logical to physical (L2P) table indicative of logical addresses and associated physical addresses of the data. Additionally, the data storage device includes a volatile memory to store one or more bins. Each bin is indicative of a subset of entries in the L2P table. Further, the data storage device includes a controller to allocate a bin in the volatile memory, write a plurality of updates to a subset of entries of the L2P table to the bin, and write the bin to the L2P table in a single write operation. Other embodiments are also described and claimed.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: January 7, 2020
    Assignee: Intel Corporation
    Inventors: Peng Li, Anand S. Ramalingam, William K. Lui, Sanjeev N. Trika
  • Publication number: 20200004012
    Abstract: A camera device with anti-ghosting and anti-flare properties includes a printed circuit board; an image sensor mounted on the printed circuit board; and a supporting bracket fixed on the printed circuit board. The supporting bracket includes a supporting plate and perpendicular side wall. The supporting plate and the side wall together form a receiving room covering the image sensor, the supporting plate is opened to form a step portion. The step portion comprises a matte top bearing surface, and a protecting sheet fixed on the matte top bearing surface.
    Type: Application
    Filed: December 25, 2018
    Publication date: January 2, 2020
    Inventors: SHUAI-PENG LI, SHIN-WEN CHEN, KUN LI, LONG-FEI ZHANG
  • Publication number: 20200006192
    Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; a die having a first surface and an opposing second surface, wherein the first surface of the die is coupled to the second surface of the package substrate; a cooling apparatus thermally coupled to the second surface of the die; and a thermal interface material (TIM) between the second surface of the die and the cooling apparatus, wherein the TIM includes an indium alloy having a liquidus temperature equal to or greater than about 245 degrees Celsius.
    Type: Application
    Filed: June 27, 2018
    Publication date: January 2, 2020
    Applicant: Intel Corporation
    Inventors: Peng Li, Sergio Antonio Chan Arguedas, Yongmei Liu, Deepak Goyal, Ken Hackenberg
  • Patent number: 10522834
    Abstract: A multiple-element composite material for negative electrodes, a preparation method therefor, and a lithium-ion battery using the negative electrode material. The lithium-ion battery uses multiple-element composite material for negative electrodes has a core-shell structure containing multiple shell layers. The inner core consists of graphite and nano-active matter coating the surface of the graphite. The outer layers of the inner core are in order: the first shell layer is of an electrically conductive carbon material, the second shell layer is of a nano-active matter, and the third shell layer is an electrically conductive carbon material coating layer.
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: December 31, 2019
    Assignee: Shenzhen BTR New Energy Materials Inc.
    Inventors: Min Yue, Peng He, Sheng Li, Jianguo Ren, Youyuan Huang
  • Patent number: 10522649
    Abstract: A method of fabricating air gap spacers is provided. The method includes forming gate structures to extend upwardly from a substrate with source or drain (S/D) regions disposed between the gate structures and with contact trenches defined above the S/D regions and between the gate structures. The method further includes disposing contacts in the contact trenches. The method also includes configuring the contacts to define open-ended air gap spacer trenches with the gate structures. In addition, the method includes forming a cap over the open-ended air gap spacer trenches to define the open-ended air gap spacer trenches as air gap spacers. The gate structures have an initial structure prior to and following the disposing and the configuring of the contacts and prior to and following the forming of the cap.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: December 31, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Choonghyun Lee, Juntao Li, Heng Wu, Peng Xu
  • Patent number: 10522442
    Abstract: An enclosed digital power amplifier has features for accommodating thermal cycling. The digital power amplifier includes an amplifier board and a controller board, both of which are in a protective housing. The amplifier board includes electronic components mounted on a copper circuit layer that is disposed on a dielectric layer that is disposed on an aluminum substrate layer. The housing includes slotted mounting projections that extend from sidewalls to isolate fasteners from the aluminum substrate layer, and thereby accommodate expansion of the aluminum substrate layer while the digital power amplifier is secured to a surface by the fasteners. Bottom edges of the sidewalls contact a top outer edge of the amplifier board. The mounting projections contact side outer edges of the first circuit board.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: December 31, 2019
    Assignee: Performance Motion Devices, Inc.
    Inventors: Emanuel Gustav Lewin, Peter Fransiscus Vandermeulen, Peng Li, David Chanan Horovitch Shmelzer, Ahmad Radey Shouman, Guy Richard Raiti
  • Patent number: 10520678
    Abstract: A high-density fiber array unit includes a plurality of substrates arranged and connected in an array, a side plate arranged at one side of the plurality of substrates and connected to one of the plurality of substrates, and a plurality of fibers. Each substrate comprises a first surface and a second surface opposing the first surface, and the first surface defines positioning grooves. The side plate is connected to the first surface of one of the substrates, and each fiber can be fixed to and held by a positioning groove. A fiber array apparatus including the fiber array unit is also provided.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: December 31, 2019
    Assignee: Fujin Precision Industrial (Jincheng)Co., Ltd.
    Inventors: Wu-Kuang Chen, Shin-Lo Chia, Zhi-Ming Li, Le-Peng Wei