Patents by Inventor Peng Ong

Peng Ong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200268565
    Abstract: A disposable absorbent article such as a diaper, pant diaper, a sanitary pant or incontinence garment, intended to be worn around the waist of a wearer is provided. The absorbent article has a chassis having a front portion, a back portion and a crotch portion therebetween. The absorbent article optionally has one or more fastening tabs attached to the back or front portion of the chassis. The absorbent article has an absorbent core secured to the chassis in at least the crotch portion. The absorbent article is provided with a QR-code on a garment facing-side thereof and on a carrier material in or on at least one of the front portion, back portion and/or on the one or more fastening tabs. The carrier material has a Gurley stiffness of 8 mgf or more.
    Type: Application
    Filed: September 7, 2017
    Publication date: August 27, 2020
    Applicant: Essity Hygiene and Health Aktiebolag
    Inventors: Wen Shiuan Ling, Chow Peng Ong, Huey Chyi U
  • Patent number: 10302694
    Abstract: One example includes a test system that includes a printed circuit board and a switching interposer board. The switching interposer board is comprised of a probe point, a first bus, a second bus, and a set of switches. Each switch includes a first terminal, a second terminal, and a third terminal, the first terminal being coupled to a respective pin of an integrated circuit device, the second terminal being coupled to the first bus, and the third terminal being coupled to the second bus. Each of the set of switches have a first state that selectively couples a pair of the pins of the integrated circuit device to each other through the first bus during a short test, and a second state that selectively couples at least one of the pins of the integrated circuit device to the probe point through the second bus during a voltage level spike test.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: May 28, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Chee Peng Ong, Hoon Siong Chia
  • Publication number: 20180180668
    Abstract: One example includes a test system that includes a printed circuit board and a switching interposer board. The switching interposer board is comprised of a probe point, a first bus, a second bus, and a set of switches. Each switch includes a first terminal, a second terminal, and a third terminal, the first terminal being coupled to a respective pin of an integrated circuit device, the second terminal being coupled to the first bus, and the third terminal being coupled to the second bus. Each of the set of switches have a first state that selectively couples a pair of the pins of the integrated circuit device to each other through the first bus during a short test, and a second state that selectively couples at least one of the pins of the integrated circuit device to the probe point through the second bus during a voltage level spike test.
    Type: Application
    Filed: December 27, 2016
    Publication date: June 28, 2018
    Inventors: CHEE PENG ONG, HOON SIONG CHIA
  • Patent number: 9207278
    Abstract: An electronic package that has an array of pins may be tested for shorts and continuity in a parallel manner. The array of pins are allocated to four or more groups of pins such that each pin in each group is not adjacent to a pin from its own group of pins. One of the groups of pins is tested for continuity while placing a reference voltage level on all of the pins in the other groups of pins. A separate current source is coupled to each pin and a resultant voltage is measured. A short between one of the pins in the first group and a pin in one of the other groups can be detected when the resultant voltage on one of the pins in the first group is approximately equal to the reference voltage. Group-wise testing is repeated until all groups have been tested.
    Type: Grant
    Filed: March 22, 2013
    Date of Patent: December 8, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Hoon Siong Chia, Chee Peng Ong
  • Patent number: 9140751
    Abstract: An electronic package having multiple pins may be tested in parallel for output short circuit current by simulating a direct short to ground by simultaneously connecting multiple output pins directly to ground in order to active a current limiter associated with each of the output pins. The pins are then connected to a resistive connection to ground via a set of resistors; the direct ground is then removed, such that the current limiter associated with each of the output pins remains activated. A voltage drop across each of the set of resistors is measured simultaneously. An output short circuit current fault is indicated when the voltage drop across any of the resistors exceeds a threshold value corresponding to a maximum output short circuit current value.
    Type: Grant
    Filed: March 27, 2013
    Date of Patent: September 22, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Chee Peng Ong, Wen Hui Woon, Benyong Zhang, Eric Lindgren
  • Publication number: 20140292361
    Abstract: An electronic package having multiple pins may be tested in parallel for output short circuit current by simulating a direct short to ground by simultaneously connecting multiple output pins directly to ground in order to active a current limiter associated with each of the output pins. The pins are then connected to a resistive connection to ground via a set of resistors; the direct ground is then removed, such that the current limiter associated with each of the output pins remains activated. A voltage drop across each of the set of resistors is measured simultaneously.
    Type: Application
    Filed: March 27, 2013
    Publication date: October 2, 2014
    Applicant: Texas Instruments Incorporated
    Inventors: Chee Peng Ong, Wen Hui Woon, Benyong Zhang, Eric Lindgren
  • Publication number: 20140285229
    Abstract: An electronic package that has an array of pins may be tested for shorts and continuity in a parallel manner. The array of pins are allocated to four or more groups of pins such that each pin in each group is not adjacent to a pin from its own group of pins. One of the groups of pins is tested for continuity while placing a reference voltage level on all of the pins in the other groups of pins. A separate current source is coupled to each pin and a resultant voltage is measured. A short between one of the pins in the first group and a pin in one of the other groups can be detected when the resultant voltage on one of the pins in the first group is approximately equal to the reference voltage. Group-wise testing is repeated until all groups have been tested.
    Type: Application
    Filed: March 22, 2013
    Publication date: September 25, 2014
    Applicant: Texas Instruments Incorporated
    Inventors: Hoon Siong Chia, Chee Peng Ong
  • Patent number: 8276104
    Abstract: A process for automated via doubling in a layout of a semiconductor device, comprising: selecting at least one cell of the layout for via doubling, wherein the at least one cell comprises at least two metal layers; selecting at least two metal layers of the at least one cell for via doubling; selecting metal/metal intersection areas out of the at least two metal layers, wherein a metal/metal intersection comprises an existing via interconnecting a plurality of metal layers; and dimensionally fitting additional vias into the selected metal/metal intersection areas, wherein the additional vias are placed into the layout.
    Type: Grant
    Filed: December 9, 2010
    Date of Patent: September 25, 2012
    Assignee: Spansion LLC
    Inventors: Gregory Sylvester Emmanuel, Hui-Peng Ong, Kian-Boon How, Joseph Lin
  • Publication number: 20120151430
    Abstract: A process for automated via doubling in a layout of a semiconductor device, comprising: selecting at least one cell of the layout for via doubling, wherein the at least one cell comprises at least two metal layers; selecting at least two metal layers of the at least one cell for via doubling; selecting metal/metal intersection areas out of the at least two metal layers, wherein a metal/metal intersection comprises an existing via interconnecting a plurality of metal layers; and dimensionally fitting additional vias into the selected metal/metal intersection areas, wherein the additional vias are placed into the layout.
    Type: Application
    Filed: December 9, 2010
    Publication date: June 14, 2012
    Inventors: Gregory Sylvester EMMANUEL, Hui-Peng ONG, Kian-Boon HOW, Joseph LIN
  • Patent number: 7915907
    Abstract: A system is provided that facilitates locating long dangling metal routes in a semiconductor chip design. The system includes mechanisms for partitioning metal features of the chip design to discover dangling metal routes that could be potential violations. The system further comprises mechanisms for determining if the dangling metal routes of the chip design exceed a length limit that could result antenna violations, undesired noise in the circuit, circuitry breakdown or the like. The system enables excessively long dangling metal routes to be allowed as exceptional cases. Machine learning is provided to receive feedback to refine the exceptional cases and enable more efficient fault detection.
    Type: Grant
    Filed: June 25, 2007
    Date of Patent: March 29, 2011
    Assignee: Spansion LLC
    Inventors: Hui Peng Ong, Chun Keong Lee, Gregory Sylvester Emmanuel
  • Publication number: 20080315906
    Abstract: A system is provided that facilitates locating long dangling metal routes in a semiconductor chip design. The system includes mechanisms for partitioning metal features of the chip design to discover dangling metal routes that could be potential violations. The system further comprises mechanisms for determining if the dangling metal routes of the chip design exceed a length limit that could result antenna violations, undesired noise in the circuit, circuitry breakdown or the like. The system enables excessively long dangling metal routes to be allowed as exceptional cases. Machine learning is provided to receive feedback to refine the exceptional cases and enable more efficient fault detection.
    Type: Application
    Filed: June 25, 2007
    Publication date: December 25, 2008
    Applicant: SPANSION LLC
    Inventors: Hui-Peng Ong, Chun-Keong Lee, Gregory Sylvester Emmanuel
  • Publication number: 20070208950
    Abstract: A method and apparatus for automatic user authentication are described. The method includes receiving information at a device, the device including a credential container; storing the information at the credential container and performing cryptographic calculations on the received information and providing the encrypted information upon request.
    Type: Application
    Filed: February 20, 2007
    Publication date: September 6, 2007
    Inventor: Peng Ong
  • Publication number: 20070050362
    Abstract: A method and system for protecting electronic files by applying a portable access control lock to each electronic file while allowing multi-user access to the protected electronic files across a distributed network is described. The portable access control lock is adapted for implementing a set of complex access control rules that include managing an audit trail for the corresponding protected electronic file.
    Type: Application
    Filed: October 21, 2005
    Publication date: March 1, 2007
    Inventors: Chee Low, Peng Ong
  • Publication number: 20060083228
    Abstract: The invention relates to a system for securing access to resources or computer systems by means of a self modifying, single use password that limits access to a system and automatically changes each time it is used. Independent computer systems, or clients, are utilized by users to generate one time passcodes to prove their identity to one or more authentication servers. Servers are used to authenticate user inputted one time passcodes, to maintain and update the status of one time passcode clients, and perform rekeying and reset operations. Middleware, an optional component, allows for the interaction between one time passcode clients and servers. Middleware allows for client rekeying and resets as well as synchronisation between the client and server.
    Type: Application
    Filed: October 20, 2004
    Publication date: April 20, 2006
    Inventors: Peng Ong, Sriram Ramachandran
  • Publication number: 20060080729
    Abstract: A method and system for strengthening authentication credentials for accessing any number of applications across multiple access interfaces and across multiple remote access sites is disclosed. The applications can be accessed by a set of authorized users by using multiple instances of a predictive scheme for generating and synchronizing the authentication credentials and by leveraging pre-existing infrastructure associated with the applications.
    Type: Application
    Filed: May 18, 2005
    Publication date: April 13, 2006
    Applicant: Encentuate Pte. Ltd.
    Inventors: Eng-Kiat Koh, Mok Ku, Chee Low, Peng Ong
  • Publication number: 20050210247
    Abstract: A method of authentication that provides the security of a challenge response authentication is described. The method is compatible with an existing infrastructure password-based authentication.
    Type: Application
    Filed: March 18, 2004
    Publication date: September 22, 2005
    Inventors: Peng Ong, Eng-Kiat Koh
  • Publication number: 20050182971
    Abstract: A multi-purpose user authentication card that combines the functions of one-time passcode generator, storage components and smart card components in a single compact device. A microprocessor generates the one-time passcode, which is displayed on a screen for 30-60 seconds. A smart card performs basic encryption and decryption to allow the user to gain access to a protected external resource. An independent, rechargeable power source allows the card to switch between an active mode, a standby mode and an off mode.
    Type: Application
    Filed: February 12, 2004
    Publication date: August 18, 2005
    Inventors: Peng Ong, Chua Joo, Chin Vui
  • Publication number: 20040156617
    Abstract: A video recorder has a source of a digital stream representing a video signal and a medium interface for recording the digital stream as a recording among a plurality of recordings. An indicator of the video signal standard is also recorded for each recording. When a change in the video standard is detected, a new recording is started with an indicator of the new video standard attached.
    Type: Application
    Filed: February 3, 2004
    Publication date: August 12, 2004
    Inventors: Kwong Heng Kwok, Chuan Peng Ong