Patents by Inventor Peng Ou
Peng Ou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11961939Abstract: A method of manufacturing a light-emitting device, including: providing a substrate structure including a top surface; forming a precursor layer on the top surface; removing a portion of the precursor layer and a portion of the substrate from the top surface to form a base portion and a plurality of protrusions regularly arranged on the base portion; forming a buffer layer on the base portion and the plurality protrusions; and forming a III-V compound cap layer on the buffer layer; wherein one of the plurality of protrusions comprises a first portion and a second portion formed on the first portion; wherein the first portion is integrated with the base portion and has a first material which is the same as that of the base portion; and wherein the buffer layer contacts side surfaces of the plurality of protrusions and a surface of the base portion.Type: GrantFiled: June 23, 2022Date of Patent: April 16, 2024Assignee: EPISTAR CORPORATIONInventors: Peng Ren Chen, Yu-Shan Chiu, Wen-Hsiang Lin, Shih-Wei Wang, Chen Ou
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Publication number: 20240070342Abstract: The present disclosure relates to the field of a stability design of pressure vessels and main bearing members of nuclear engineering, and discloses a new design method for an allowable compressive stress of an axially compressed cylinder. By introducing elastic-plastic influence parameters and cylinder structure characteristic parameters, a critical buckling stress values of axially compressed cylinders under different buckling failure modes and a critical buckling stress reduction factor considering the influence of initial defects are obtained. At the same time, a design safety factor of the axially compressed cylinder is given, and a new calculation flow for the allowable compressive stress of the axially compressed cylinder is put forward. The present method is of great significance to promote the development of large-scale and lightweight axially compressed cylinders in engineering.Type: ApplicationFiled: October 24, 2023Publication date: February 29, 2024Inventors: Zhiping CHEN, Peng JIAO, Hao MIAO, Haiyang OU, Yao ZHU
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Patent number: 10831541Abstract: Example embodiments of the present disclosure provide methods and devices for optimizing performance of hardware accelerators. The accelerator device may detect status information of a current acceleration task being executed. The detected status information is provided to a host associated with the accelerator device. The host makes preparation for a subsequent acceleration task based on the status information before termination of the current running acceleration task. The accelerator device may execute the subsequent acceleration task based on the preparation. In this way, the performance of hardware accelerator is optimized.Type: GrantFiled: July 19, 2018Date of Patent: November 10, 2020Assignee: International Business Machines CorporationInventors: Yang Liu, Yong Lu, Peng Ou, Hong Bo Peng
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Patent number: 10380285Abstract: A computer program product for calculating a path delay in static timing analysis (STA) for a circuit design includes determining a connectivity between a first device and a second device in a path of the circuit design, generating a delay constraint associated with the first device and the second device based on the connectivity, the delay constraint specifying a correlation between a first device delay of the first device and a second device delay of the second device, and calculating a path delay of the path based on the first device delay and the second device delay that satisfies the delay constraint.Type: GrantFiled: February 13, 2017Date of Patent: August 13, 2019Assignee: International Business Machines CorporationInventors: Hongwei Dai, Yang Liu, Jia Niu, Peng Ou
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Publication number: 20180321978Abstract: Example embodiments of the present disclosure provide methods and devices for optimizing performance of hardware accelerators. The accelerator device may detect status information of a current acceleration task being executed. The detected status information is provided to a host associated with the accelerator device. The host makes preparation for a subsequent acceleration task based on the status information before termination of the current running acceleration task. The accelerator device may execute the subsequent acceleration task based on the preparation. In this way, the performance of hardware accelerator is optimized.Type: ApplicationFiled: July 19, 2018Publication date: November 8, 2018Inventors: Yang Liu, Yong Lu, Peng Ou, Hong Bo Peng
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Patent number: 10055255Abstract: Example embodiments of the present disclosure provide methods and devices for optimizing performance of hardware accelerators. The accelerator device may detect status information of a current acceleration task being executed. The detected status information is provided to a host associated with the accelerator device. The host makes preparation for a subsequent acceleration task based on the status information before termination of the current running acceleration task. The accelerator device may execute the subsequent acceleration task based on the preparation. In this way, the performance of hardware accelerator is optimized.Type: GrantFiled: April 14, 2016Date of Patent: August 21, 2018Assignee: International Business Machines CorporationInventors: Yang Liu, Yong Lu, Peng Ou, Hong Bo Peng
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Publication number: 20170300362Abstract: Example embodiments of the present disclosure provide methods and devices for optimizing performance of hardware accelerators. The accelerator device may detect status information of a current acceleration task being executed. The detected status information is provided to a host associated with the accelerator device. The host makes preparation for a subsequent acceleration task based on the status information before termination of the current running acceleration task. The accelerator device may execute the subsequent acceleration task based on the preparation. In this way, the performance of hardware accelerator is optimized.Type: ApplicationFiled: April 14, 2016Publication date: October 19, 2017Inventors: Yang Liu, Yong Lu, Peng Ou, Hong Bo Peng
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Publication number: 20170154143Abstract: A computer program product for calculating a path delay in static timing analysis (STA) for a circuit design includes determining a connectivity between a first device and a second device in a path of the circuit design, generating a delay constraint associated with the first device and the second device based on the connectivity, the delay constraint specifying a correlation between a first device delay of the first device and a second device delay of the second device, and calculating a path delay of the path based on the first device delay and the second device delay that satisfies the delay constraint.Type: ApplicationFiled: February 13, 2017Publication date: June 1, 2017Inventors: Hongwei Dai, Yang Liu, Jia Niu, Peng Ou
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Patent number: 9633148Abstract: A method of for calculating a path delay in static timing analysis (STA) for a circuit design includes determining a connectivity between a first device and a second device in a path of the circuit design, generating a delay constraint associated with the first device and the second device based on the connectivity, the delay constraint specifying a correlation between a first device delay of the first device and a second device delay of the second device, and calculating a path delay of the path based on the first device delay and the second device delay that satisfies the delay constraint.Type: GrantFiled: September 15, 2015Date of Patent: April 25, 2017Assignee: International Business Machines CorporationInventors: Hongwei Dai, Yang Liu, Jia Niu, Peng Ou
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Publication number: 20160154915Abstract: A method of for calculating a path delay in static timing analysis (STA) for a circuit design includes determining a connectivity between a first device and a second device in a path of the circuit design, generating a delay constraint associated with the first device and the second device based on the connectivity, the delay constraint specifying a correlation between a first device delay of the first device and a second device delay of the second device, and calculating a path delay of the path based on the first device delay and the second device delay that satisfies the delay constraint.Type: ApplicationFiled: September 15, 2015Publication date: June 2, 2016Inventors: Hongwei Dai, Yang Liu, Jia Niu, Peng Ou
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Publication number: 20160063158Abstract: The present invention discloses a method and device for simulating a circuit design. The method includes identifying at least one Sequential-cell-To-Sequential-cell (S2S) block in the circuit design, wherein the S2S block includes at least one input sequential cell, at least one output sequential cell, and an intermediate portion between the input sequential cell and the output sequential cell, wherein the intermediate portion includes at least one combinational cell; determining logic characteristics and timing characteristics of the intermediate portion; and replacing the intermediate portion with a functional module having the logic characteristics and the timing characteristics to generate a simplified circuit design to be used in simulation. With the technical solution according to embodiments of the invention, time needed in simulation is shortened.Type: ApplicationFiled: June 24, 2015Publication date: March 3, 2016Inventors: Peng Fei Gou, De Xian Li, Yu Fei Li, Yang Liu, Peng Ou
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Patent number: 8831431Abstract: An apparatus comprising an optical transceiver module. The apparatus also includes an interface coupled to the optical transceiver and comprising a plurality of pins. The interface is configured to communicate a burst data word at a data rate of about one data word within about a shortest burst time based on multiplexing one of a plurality of control and/or monitoring signals onto one of the plurality of pins.Type: GrantFiled: April 5, 2011Date of Patent: September 9, 2014Assignee: Futurewei Technologies, Inc.Inventors: Peng Ou, Zebin Li, Yuanqiu Luo
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Publication number: 20130290718Abstract: The present invention relates to network security technology, and particularly relates to a mobile storage device for data processing in security, and a data processing system comprising the mobile storage device, and a data processing method using the data processing system. According to the present invention, the mobile storage device for data processing in security comprising: at least one memory for storing a secret key; an interface circuit; and a processing unit for communicating with a remote device via the interface circuit and performing security processing and application processing, the security processing including data encryption and decryption with the secret key.Type: ApplicationFiled: October 26, 2011Publication date: October 31, 2013Applicant: CHINA UNIONPAY CO., LTD.Inventors: Xiao Zhuang, Zhijun Lu, Shuo He, Hongwen Meng, Peng Ou
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Patent number: 8245095Abstract: An apparatus comprising a Forward Error Correction (FEC) processor coupled to an optical receiver, wherein the FEC processor is configured to compare a plurality of received blocks to a plurality of FEC codeword blocks comprising a plurality of parity blocks, and upon detecting a misaligned block in the received blocks, compare at least some of the remaining received blocks to the parity blocks. Also included is an apparatus comprising at least one component configured to implement a method comprising receiving a plurality of blocks, wherein the quantity of received blocks is equal to a quantity of blocks in a FEC codeword, selecting one of the received blocks, determining whether the selected block is aligned with the FEC codeword, and determining whether the remaining blocks correspond to the FEC codeword when the selected block is not aligned with the FEC codeword.Type: GrantFiled: February 12, 2009Date of Patent: August 14, 2012Assignee: Futurewei Technologies, Inc.Inventors: Peng Ou, Frank J. Effenberger
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Publication number: 20110249968Abstract: An apparatus comprising an optical transceiver module. The apparatus also includes an interface coupled to the optical transceiver and comprising a plurality of pins.Type: ApplicationFiled: April 5, 2011Publication date: October 13, 2011Applicant: FUTUREWEI TECHNOLOGIES, INC.Inventors: Peng Ou, Zebin Li, Yuanqiu Luo
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Publication number: 20090276681Abstract: An apparatus comprising a Forward Error Correction (FEC) processor coupled to an optical receiver, wherein the FEC processor is configured to compare a plurality of received blocks to a plurality of FEC codeword blocks comprising a plurality of parity blocks, and upon detecting a misaligned block in the received blocks, compare at least some of the remaining received blocks to the parity blocks. Also included is an apparatus comprising at least one component configured to implement a method comprising receiving a plurality of blocks, wherein the quantity of received blocks is equal to a quantity of blocks in a FEC codeword, selecting one of the received blocks, determining whether the selected block is aligned with the FEC codeword, and determining whether the remaining blocks correspond to the FEC codeword when the selected block is not aligned with the FEC codeword.Type: ApplicationFiled: February 12, 2009Publication date: November 5, 2009Applicant: FUTUREWEI TECHNOLOGIES, INC.Inventors: Peng Ou, Frank J. Effenberger