Abstract: A content search method performed by a computer device includes obtaining a search term from a content input area of a first application interface, and displaying a candidate search engine; and switching from the first application interface to a second application interface in response to a selection operation on a target search engine in the candidate search engine. A search result, obtained after a searching process of the search term on the target search engine, is displayed on the second application interface.

Abstract: Provided are a photovoltaic facility and a method for assembling a frame of a photovoltaic module. The photovoltaic facility includes: a clamp, a color steel tile, a photovoltaic module, and a connecting member. The clamp is connected to the color steel tile and includes a clamping body. The photovoltaic module is located on one side of the clamping body and is connected to the clamping body through the connecting member. The photovoltaic module includes a laminate and a frame. The frame is connected to a back side of the laminate and has an opening. The connecting member extends into the opening and abuts against a sidewall of the opening. The photovoltaic module is connected to the color steel tile through the clamp.

Abstract: Provided are a photovoltaic module and a photovoltaic facility. The photovoltaic module includes a laminate and a frame. The frame includes a first portion, a second portion, and a third portion. The second portion and the third portion are respectively connected to two ends of the first portion. The second portion and the third portion extend along a first direction, and the second portion is fixedly connected to a back surface of the laminate, or the second portion and the third portion extend along a third direction, and the first portion is fixedly connected to the back surface of the laminate. The frame supports the laminate.

Abstract: Example wireless charging systems are provided. For example, an example wireless charging system includes a plurality of power receiving coils secured on a receiver inner curved surface of a power receiver curved portion; and a charging relay component comprising ferromagnetic material and defining a receiver relay curved surface.

Abstract: Example embodiments of the present disclosure provide methods and devices for optimizing performance of hardware accelerators. The accelerator device may detect status information of a current acceleration task being executed. The detected status information is provided to a host associated with the accelerator device. The host makes preparation for a subsequent acceleration task based on the status information before termination of the current running acceleration task. The accelerator device may execute the subsequent acceleration task based on the preparation. In this way, the performance of hardware accelerator is optimized.

Abstract: A computer program product for calculating a path delay in static timing analysis (STA) for a circuit design includes determining a connectivity between a first device and a second device in a path of the circuit design, generating a delay constraint associated with the first device and the second device based on the connectivity, the delay constraint specifying a correlation between a first device delay of the first device and a second device delay of the second device, and calculating a path delay of the path based on the first device delay and the second device delay that satisfies the delay constraint.

Abstract: Example embodiments of the present disclosure provide methods and devices for optimizing performance of hardware accelerators. The accelerator device may detect status information of a current acceleration task being executed. The detected status information is provided to a host associated with the accelerator device. The host makes preparation for a subsequent acceleration task based on the status information before termination of the current running acceleration task. The accelerator device may execute the subsequent acceleration task based on the preparation. In this way, the performance of hardware accelerator is optimized.

Abstract: Example embodiments of the present disclosure provide methods and devices for optimizing performance of hardware accelerators. The accelerator device may detect status information of a current acceleration task being executed. The detected status information is provided to a host associated with the accelerator device. The host makes preparation for a subsequent acceleration task based on the status information before termination of the current running acceleration task. The accelerator device may execute the subsequent acceleration task based on the preparation. In this way, the performance of hardware accelerator is optimized.

Abstract: Example embodiments of the present disclosure provide methods and devices for optimizing performance of hardware accelerators. The accelerator device may detect status information of a current acceleration task being executed. The detected status information is provided to a host associated with the accelerator device. The host makes preparation for a subsequent acceleration task based on the status information before termination of the current running acceleration task. The accelerator device may execute the subsequent acceleration task based on the preparation. In this way, the performance of hardware accelerator is optimized.

Abstract: A computer program product for calculating a path delay in static timing analysis (STA) for a circuit design includes determining a connectivity between a first device and a second device in a path of the circuit design, generating a delay constraint associated with the first device and the second device based on the connectivity, the delay constraint specifying a correlation between a first device delay of the first device and a second device delay of the second device, and calculating a path delay of the path based on the first device delay and the second device delay that satisfies the delay constraint.

Abstract: A method of for calculating a path delay in static timing analysis (STA) for a circuit design includes determining a connectivity between a first device and a second device in a path of the circuit design, generating a delay constraint associated with the first device and the second device based on the connectivity, the delay constraint specifying a correlation between a first device delay of the first device and a second device delay of the second device, and calculating a path delay of the path based on the first device delay and the second device delay that satisfies the delay constraint.

Abstract: A method of for calculating a path delay in static timing analysis (STA) for a circuit design includes determining a connectivity between a first device and a second device in a path of the circuit design, generating a delay constraint associated with the first device and the second device based on the connectivity, the delay constraint specifying a correlation between a first device delay of the first device and a second device delay of the second device, and calculating a path delay of the path based on the first device delay and the second device delay that satisfies the delay constraint.

Abstract: The present invention discloses a method and device for simulating a circuit design. The method includes identifying at least one Sequential-cell-To-Sequential-cell (S2S) block in the circuit design, wherein the S2S block includes at least one input sequential cell, at least one output sequential cell, and an intermediate portion between the input sequential cell and the output sequential cell, wherein the intermediate portion includes at least one combinational cell; determining logic characteristics and timing characteristics of the intermediate portion; and replacing the intermediate portion with a functional module having the logic characteristics and the timing characteristics to generate a simplified circuit design to be used in simulation. With the technical solution according to embodiments of the invention, time needed in simulation is shortened.

Abstract: An apparatus comprising an optical transceiver module. The apparatus also includes an interface coupled to the optical transceiver and comprising a plurality of pins. The interface is configured to communicate a burst data word at a data rate of about one data word within about a shortest burst time based on multiplexing one of a plurality of control and/or monitoring signals onto one of the plurality of pins.

Abstract: The present invention relates to network security technology, and particularly relates to a mobile storage device for data processing in security, and a data processing system comprising the mobile storage device, and a data processing method using the data processing system. According to the present invention, the mobile storage device for data processing in security comprising: at least one memory for storing a secret key; an interface circuit; and a processing unit for communicating with a remote device via the interface circuit and performing security processing and application processing, the security processing including data encryption and decryption with the secret key.

Abstract: An apparatus comprising a Forward Error Correction (FEC) processor coupled to an optical receiver, wherein the FEC processor is configured to compare a plurality of received blocks to a plurality of FEC codeword blocks comprising a plurality of parity blocks, and upon detecting a misaligned block in the received blocks, compare at least some of the remaining received blocks to the parity blocks. Also included is an apparatus comprising at least one component configured to implement a method comprising receiving a plurality of blocks, wherein the quantity of received blocks is equal to a quantity of blocks in a FEC codeword, selecting one of the received blocks, determining whether the selected block is aligned with the FEC codeword, and determining whether the remaining blocks correspond to the FEC codeword when the selected block is not aligned with the FEC codeword.

Abstract: An apparatus comprising an optical transceiver module. The apparatus also includes an interface coupled to the optical transceiver and comprising a plurality of pins.

Abstract: An apparatus comprising a Forward Error Correction (FEC) processor coupled to an optical receiver, wherein the FEC processor is configured to compare a plurality of received blocks to a plurality of FEC codeword blocks comprising a plurality of parity blocks, and upon detecting a misaligned block in the received blocks, compare at least some of the remaining received blocks to the parity blocks. Also included is an apparatus comprising at least one component configured to implement a method comprising receiving a plurality of blocks, wherein the quantity of received blocks is equal to a quantity of blocks in a FEC codeword, selecting one of the received blocks, determining whether the selected block is aligned with the FEC codeword, and determining whether the remaining blocks correspond to the FEC codeword when the selected block is not aligned with the FEC codeword.