Abstract: A reconfigurable processor chip includes: a plurality of reconfigurable processing elements based on distributed storage, components of the reconfigurable processing elements being logically interconnected. The components include: a reconfigurable computing component configured to calculate data; a data flow controller using a data flow driving mode, the data flow driving mode is configured to control start and end of a computing task and a data transmission task based on data flow information about the computing task and message transferring of upstream and downstream reconfigurable processing elements; a distributed memory configured to implement data storage of a corresponding reconfigurable processing element; and a programmable data routing element configured to implement communication between the plurality of reconfigurable processing elements to control a direction of a data packet, and implement flexible transmission of the data packet.

Abstract: A data loading and storage system includes a storage module, a buffering module, a control module, a plurality of data loading modules, a plurality of data storage modules and a multi-core processor array module. The data is continuously stored in a DDR, and the data computed by the multi-core processor may be arranged continuously or be arranged according to a certain rule. After DMA reads the data into the DATA_BUF module by a BURST mode, in order to support fast loading of the data into the multi-core processor array, the data loading modules (i.e., load modules) are designed. In order to quickly store the computed result of the multi-core processor array into the (DATA_BUF module according to a certain rule, the data storage modules (i.e., store module) are designed.

Abstract: A bridge drive system, including a housing, a motor, a speed reduction mechanism, and a shaft assembly. The housing has first and second spaces separated from each other. The motor is in the first space, and the speed reduction mechanism is in the second space. The shaft assembly has an oil inlet and an oil outlet which are both located in the second space. An oil passage extending from the oil inlet into the first space and then returning to the oil outlet is formed inside the shaft assembly so that oil from the second space can flow from the oil inlet into the oil passage to cool a rotor and then return to the second space from the oil outlet. In this way, the cooling performance of a motor is improved, improving its performance and reducing heat resistance requirements of each component.

Abstract: An image correction method includes: capturing speckle patterns on two planes at different distances to obtain a first image of speckle projected on a first plane and a second image of speckle projected on a second plane; matching the first image with the second image to obtain sub-pixel matching points; obtaining, based on first physical coordinates of the sub-pixel matching points on the first image and second physical coordinates of the sub-pixel matching points on the second image, a mapping matrix between the first and second physical coordinates; obtaining a direction vector of a center of the speckle projector in a camera reference frame according to the mapping matrix; adjusting coordinate axis directions of the camera reference frame to align a horizontal axis direction with the direction vector, updating an imaging matrix of the camera; and mapping a target scene image through the imaging matrix to obtain a corrected image.

Abstract: Provided are a memory coupled compiling method and system of a reconfigurable chip. The memory coupled compiling method includes: acquiring a cycle number of a data flow graph (DFG); acquiring a linear transformation vector of the cycle number through a mapping time difference; determining whether a linear array of the linear transformation vector is acquired by a heuristic algorithm; acquiring a memory mapping result through a current DFG or acquiring a cycle number of the current DFG until the linear array is acquired, depending on the determination result.

Abstract: A computing array includes a plurality of process element groups, and each of the plurality of the process element groups includes four process elements arranged in two rows and two columns and a merging unit. Each of the four process elements includes an input subunit; a fetch and decode subunit configured to obtain and compile the instruction to output a logic computing type; an operation subunit configured to obtain computing result data according to the logic computing type and the operation data; an output subunit configured to output the computing result data. The merging unit is connected to the output subunit of each of the four process elements, and configured to receive the computing result data output by the output subunit of each of the four process elements, merge the computing result data and output the merged computing result data.

Abstract: The disclosure provides a method for distributing instructions in a reconfigurable processor. The reconfigurable processor includes an instruction fetch module, an instruction sync control module and an instruction queue module. The method includes: configuring a format of a Memory Sync ID Table of each instruction type, obtaining a first memory identification field and a second memory identification field of each instruction, obtaining one-hot encodings of first and second memory identification fields, obtaining a sync table and executing each instruction of a plurality of to-be-run instructions.

Abstract: A mapping method for a reconfigurable array, including: Si obtaining and analyzing a DDG; providing an initial interval; obtaining a reconfigurable architecture; copying the first adjacency matrix and the second adjacency matrix to form a mapping space; establishing an integer linear programming model, and mapping, with the integer linear programming model, a processing vertex, an intra-cycle edge, and an inter-cycle edge in the DDG, to the mapping space, respectively; obtaining a mapping relationship from the processing vertex and the edge in the DDG to the processing element and the link of extended TS_max layers; and generating configuration information by the mapping relationship modulo the initial interval.

Abstract: An instruction scheduling method and an instruction scheduling system for a reconfigurable array processor. The method includes: determining whether a fan-out of a vertex in a data flow graph (DFG) is less than an actual interconnection number of a processing unit in a reconfigurable array; establishing a corresponding relationship between the vertex and a correlation operator of the processing unit; introducing a register to a directed edge, acquiring a retiming value of each vertex; arranging instructions in such a manner that retiming values of the instruction vertexes are in ascending order, and acquiring transmission time and scheduling order of the instructions; folding the DFG, placing an instruction to an instruction vertex; inserting a register and acquiring a current DFG; and acquiring a common maximum subset of the current DFG and the reconfigurable array by a maximum clique algorithm, and distributing the instructions.

Abstract: The present disclosure provides a processor array and a multiple-core processor. The processor array includes a plurality of processing elements arranged in a two-dimensional array, a plurality of first load units correspondingly arranged and connected to the processing elements of the first edge row, respectively, a plurality of second load units correspondingly arranged and connected to the processing elements of the first edge column, respectively, a plurality of first store units correspondingly arranged and connected to the processing elements of the second edge column, respectively, a plurality of second store units correspondingly arranged and connected to the processing elements of the second edge row, respectively.

Abstract: A data storage method includes: obtaining memory banks of arithmetic data; generating undetermined memory bank numbers of the memory banks sequentially; scanning storage dimensions of the arithmetic data to obtain the undetermined memory bank numbers, filling elements to make the undetermined memory bank numbers continuous if the undetermined memory bank numbers of two adjacent dimensions are not continuous; taking as a current transformation vector through a greedy algorithm a determined transformation vector where conflict is least and the number of the filling elements is smallest; generating current memory bank numbers of the memory banks according to the current transformation vector; converting each of the current memory bank numbers into a physical storage bank address through an offset function to obtain a corresponding internal offset address; and storing the arithmetic data into the memory banks according to the current memory bank numbers and the internal offset addresses.

Abstract: The disclosure provides a method and apparatus for processing sparse data. The method is applied to a reconfigurable processor that includes a PE array, and the PE array includes P×Q PE units. The method includes: dividing a sparse weight matrix to be calculated into at least one unit block; grouping a plurality of unit blocks into a computing group; and obtaining an effective weight address corresponding to each effective weight in the computing group.

Abstract: The disclosure provides a method for distributing instructions in a reconfigurable processor. The reconfigurable processor includes an instruction fetch module, an instruction sync control module and an instruction queue module. The method includes: configuring a format of a Memory Sync ID Table of each instruction type, obtaining a first memory identification field and a second memory identification field of each instruction, obtaining one-hot encodings of first and second memory identification fields, obtaining a sync table and executing each instruction of a plurality of to-be-run instructions.

Abstract: An instruction scheduling method and an instruction scheduling system for a reconfigurable array processor. The method includes: determining whether a fan-out of a vertex in a data flow graph (DFG) is less than an actual interconnection number of a processing unit in a reconfigurable array; establishing a corresponding relationship between the vertex and a correlation operator of the processing unit; introducing a register to a directed edge, acquiring a retiming value of each vertex; arranging instructions in such a manner that retiming values of the instruction vertexes are in ascending order, and acquiring transmission time and scheduling order of the instructions; folding the DFG, placing an instruction to an instruction vertex; inserting a register and acquiring a current DFG; and acquiring a common maximum subset of the current DFG and the reconfigurable array by a maximum clique algorithm, and distributing the instructions.

Abstract: Provided are a memory coupled compiling method and system of a reconfigurable chip. The memory coupled compiling method includes: acquiring a cycle number of a data flow graph (DFG); acquiring a linear transformation vector of the cycle number through a mapping time difference; determining whether a linear array of the linear transformation vector is acquired by a heuristic algorithm; acquiring a memory mapping result through a current DFG or acquiring a cycle number of the current DFG until the linear array is acquired, depending on the determination result.

Abstract: A data loading and storage system includes a storage module, a buffering module, a control module, a plurality of data loading modules, a plurality of data storage modules and a multi-core processor array module. The data is continuously stored in a DDR, and the data computed by the multi-core processor may be arranged continuously or be arranged according to a certain rule. After DMA reads the data into the DATA_BUF module by a BURST mode, in order to support fast loading of the data into the multi-core processor array, the data loading modules (i.e., load modules) are designed. In order to quickly store the computed result of the multi-core processor array into the (DATA_BUF module according to a certain rule, the data storage modules (i.e., store module) are designed.

Abstract: A data storage method includes: obtaining memory banks of arithmetic data; generating undetermined memory bank numbers of the memory banks sequentially; scanning storage dimensions of the arithmetic data to obtain the undetermined memory bank numbers, filling elements to make the undetermined memory bank numbers continuous if the undetermined memory bank numbers of two adjacent dimensions are not continuous; taking as a current transformation vector through a greedy algorithm a determined transformation vector where conflict is least and the number of the filling elements is smallest; generating current memory bank numbers of the memory banks according to the current transformation vector; converting each of the current memory bank numbers into a physical storage bank address through an offset function to obtain a corresponding internal offset address; and storing the arithmetic data into the memory banks according to the current memory bank numbers and the internal offset addresses.

Abstract: The present disclosure provides a processor array and a multiple-core processor. The processor array includes a plurality of processing elements arranged in a two-dimensional array, a plurality of first load units correspondingly arranged and connected to the processing elements of the first edge row, respectively, a plurality of second load units correspondingly arranged and connected to the processing elements of the first edge column, respectively, a plurality of first store units correspondingly arranged and connected to the processing elements of the second edge column, respectively, a plurality of second store units correspondingly arranged and connected to the processing elements of the second edge row, respectively.

Abstract: A computing array includes a plurality of process element groups, and each of the plurality of the process element groups includes four process elements arranged in two rows and two columns and a merging unit. Each of the four process elements includes an input subunit; a fetch and decode subunit configured to obtain and compile the instruction to output a logic computing type; an operation subunit configured to obtain computing result data according to the logic computing type and the operation data; an output subunit configured to output the computing result data. The merging unit is connected to the output subunit of each of the four process elements, and configured to receive the computing result data output by the output subunit of each of the four process elements, merge the computing result data and output the merged computing result data.

Abstract: A mapping method for a reconfigurable array, including: Si obtaining and analyzing a DDG; providing an initial interval; obtaining a reconfigurable architecture; copying the first adjacency matrix and the second adjacency matrix to form a mapping space; establishing an integer linear programming model, and mapping, with the integer linear programming model, a processing vertex, an intra-cycle edge, and an inter-cycle edge in the DDG, to the mapping space, respectively; obtaining a mapping relationship from the processing vertex and the edge in the DDG to the processing element and the link of extended TS_max layers; and generating configuration information by the mapping relationship modulo the initial interval.