Abstract: This application relates to a processing method for configuring a check pin of a memory performed by a computer device. The method includes: receiving a first data signal and a sampling pulse signal returned by a check pin in a target memory; time-shifting each first data signal through a delay circuit to align a target level value in each first data signal after the time shift with the sampling pulse signal to obtain a first delay parameter; and when receiving a second data signal returned by the check pin in the target memory, time-shifting a target data signal in each second data signal through the delay circuit to align target level values in all second data signals after the time shift to obtain a second delay parameter, determining a sampling delay parameter of the check pin based on the first delay parameter and the second delay parameter.

Abstract: This application relates to a write data signal delay control method performed by a computer device. The method includes: configuring an operating mode of a register circuit in a memory by using a host, to obtain a training register that supports reading and writing; transmitting a sample write data signal to the memory by using the host; sampling the sample write data signal based on a sampling signal by using the memory, and caching a sampled write data signal obtained from the sampling into the training register; and performing delay adjustment training on a write data delay control circuit arranged on the host based on the sample write data signal when the sampled write data signal read by the host from the training register is inconsistent with the sample write data signal.

Abstract: A power-on operation execution method and apparatus are provided. The method includes: starting a processor of the chip in response to the chip being connected to a host and a frequency of a first clock signal of the chip being switched to a stable state; receiving a reset signal transmitted from the host, the reset signal being transmitted in response to a frequency of a second clock signal of the host being switched to a stable state; and executing a power-on operation in response to the reset signal, a time point at which the frequency of the first clock signal is switched to the stable state being earlier than a time point at which the frequency of the second clock signal is switched to the stable state.