Abstract: A message-based processing system is disclosed. An input message received in the message-based processing system comprises a first indication of at least a subset of a plurality of processor elements and a second indication of a target pattern. Each of the plurality of processor elements has an addressable storage entry with a processor element address storing a processor element state. An initial address computation mode is selected from a set of address computation modes. A state value of each of the processor elements in the subset is updated based on magnitude values of respective pattern elements of the target pattern. A currently applied pattern element of the target pattern in each case determines whether to maintain a current address computation mode of the set of address computation modes or assume a next address computation mode selected from the set of address computation modes.

Abstract: A message-based processor includes a plurality of processor components. In response to receiving an input message, the message-based processor accesses a multicast pattern that includes at least one set of pattern elements. For each pattern element, a target processor component of the plurality of processor components and a target memory location are determined based on a mapping applied for the pattern element. Respective target instructions are multicast to the target processor components. The respective target instruction of each of the target processor components identifies the target memory location associated with the target processor component. A state value stored at the target memory location identified by the respective target instruction is updated by each of the target processor components to obtain an updated state value. Output messages related to the updated state values are selectively provided.

Abstract: A message-based processing system is disclosed. An input message received in the message-based processing system comprises a first indication of at least a subset of a plurality of processor elements and a second indication of a target pattern. Each of the plurality of processor elements has an addressable storage entry with a processor element address storing a processor element state. An initial address computation mode is selected from a set of address computation modes. A state value of each of the processor elements in the subset is updated based on magnitude values of respective pattern elements of the target pattern. A currently applied pattern element of the target pattern in each case determines whether to maintain a current address computation mode of the set of address computation modes or assume a next address computation mode selected from the set of address computation modes.

Abstract: A message based processor system (1) with a plurality of message based processor system cores (100) is proposed. Cores therein comprise a processor element controller that is configured to receive a message with an indication of a subset processor elements in the core to which it is directed as well as an indication of a target pattern, and to update the state value of the processor elements (Ei) in the subset in accordance with a specification of the target pattern. The processor element controller (PEC) is configurable in an address computation mode selected from a cyclic set of address computation modes, and configured to maintain its computation mode or assume a next address computation mode selected from the cyclic set dependent on a control value of a currently applied pattern element. Therewith a target pattern can efficiently specified.

Abstract: A message based processor system (1) with a plurality of message based processor system cores (100) is proposed. Cores therein comprise a processor element controller that is configured to receive a message with an indication of a subset processor elements in the core to which it is directed as well as an indication of a target pattern, and to update the state value of the processor elements (Ei) in the subset in accordance with a specification of the target pattern. The processor element controller (PEC) is configurable in an address computation mode selected from a cyclic set of address computation modes, and configured to maintain its computation mode or assume a next address computation mode selected from the cyclic set dependent on a control value of a currently applied pattern element. Therewith a target pattern can efficiently specified.

Abstract: A neuromorphic processing system (1) is disclosed comprising a plurality of neuromorphic processing clusters (100) coupled to a message exchange network (20) for exchange of event messages. A neuromorphic cluster therein comprises a message receiving facility (110) to receive event messages from the message exchange network, a message transmitting facility (120) to transmit event messages via the message exchange network and a neuromorphic processor (130) having a set of state memory entries (10 j) for storing a value representative of a neuromorphic state associated with a neuromorphic element and a computation facility (134) to update the neuromorphic state associated with neuromorphic elements that are indicated as the destination of the event message. The message receiving facility (110) and/or the message transmitting facility (120) are enhanced to enable message distribution according to a pattern.

Abstract: A heat dissipating device includes a circuit board (23), an electronic component (24) being arranged on the circuit board, a base (211) being thermally attached to the electronic component, and a plurality of fasteners (22). The circuit board defines a plurality of screw holes (230) therein. The base defines a plurality of through holes (213) corresponding to the screw holes of the circuit board. Each fastener includes a bolt (27) extending through a corresponding through hole of the base and then threadly engaging into a corresponding screw hole of the circuit board, and a coil spring (28) mounted around the bolt. The base forms a plurality of latch hooks (214) near each through hole. A bottom ring (222) of the coil spring is sandwiched between the latch hooks and the base.

Abstract: A heat dissipating device includes a circuit board (23), an electronic component (24) being arranged on the circuit board, a base (211) being thermally attached to the electronic component, and a plurality of fasteners (22). The circuit board defines a plurality of screw holes (230) therein. The base defines a plurality of through holes (213) corresponding to the screw holes of the circuit board. Each fastener includes a bolt (27) extending through a corresponding through hole of the base and then threadly engaging into a corresponding screw hole of the circuit board, and a coil spring (28) mounted around the bolt. The base forms a plurality of latch hooks (214) near each through hole. A bottom ring (222) of the coil spring is sandwiched between the latch hooks and the base.