Patents by Inventor Peng-Ren Chen

Peng-Ren Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11961939
    Abstract: A method of manufacturing a light-emitting device, including: providing a substrate structure including a top surface; forming a precursor layer on the top surface; removing a portion of the precursor layer and a portion of the substrate from the top surface to form a base portion and a plurality of protrusions regularly arranged on the base portion; forming a buffer layer on the base portion and the plurality protrusions; and forming a III-V compound cap layer on the buffer layer; wherein one of the plurality of protrusions comprises a first portion and a second portion formed on the first portion; wherein the first portion is integrated with the base portion and has a first material which is the same as that of the base portion; and wherein the buffer layer contacts side surfaces of the plurality of protrusions and a surface of the base portion.
    Type: Grant
    Filed: June 23, 2022
    Date of Patent: April 16, 2024
    Assignee: EPISTAR CORPORATION
    Inventors: Peng Ren Chen, Yu-Shan Chiu, Wen-Hsiang Lin, Shih-Wei Wang, Chen Ou
  • Publication number: 20230178399
    Abstract: Systematic fault localization systems and methods are provided which utilize computational GDS-assisted navigation to accelerate physical fault analysis to identify systematic fault locations and patterns. In some embodiments, a method includes detecting a plurality of electrical fault regions of a plurality of dies of a semiconductor wafer. Decomposed Graphic Database System (GDS) cross-layer clips are generated which are associated with the plurality of electrical fault regions. A plurality of cross-layer common patterns is identified based on the decomposed GDS cross-layer clips. Normalized differentials may be determined for each of the cross-layer common patterns, and locations of hotspots in each of the dies may be identified based on the determined normalized differentials.
    Type: Application
    Filed: February 2, 2023
    Publication date: June 8, 2023
    Inventors: Peng-Ren Chen, Wen-Hao Cheng, Jyun-Hong Chen, Chien-Hui Chen
  • Patent number: 11669957
    Abstract: A method of analyzing a semiconductor wafer includes obtaining a graphic data system (GDS) file corresponding to the semiconductor wafer, using GDS information from the GDS file to provide coordinates of a layout feature of the semiconductor wafer to an electron microscope, using the electron microscope to capture a raw image from the semiconductor wafer based on the coordinates of the layout feature, and performing a measurement operation on the raw image.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: June 6, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Peng-Ren Chen, Yi-An Huang, Jyun-Hong Chen, Wei-Chung Hu, Wen-Hao Cheng, Shiang-Bau Wang, Yung-Jung Chang
  • Patent number: 11600505
    Abstract: Systematic fault localization systems and methods are provided which utilize computational GDS-assisted navigation to accelerate physical fault analysis to identify systematic fault locations and patterns. In some embodiments, a method includes detecting a plurality of electrical fault regions of a plurality of dies of a semiconductor wafer. Decomposed Graphic Database System (GDS) cross-layer clips are generated which are associated with the plurality of electrical fault regions. A plurality of cross-layer common patterns is identified based on the decomposed GDS cross-layer clips. Normalized differentials may be determined for each of the cross-layer common patterns, and locations of hotspots in each of the dies may be identified based on the determined normalized differentials.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: March 7, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Peng-Ren Chen, Wen-Hao Cheng, Jyun-Hong Chen, Chien-Hui Chen
  • Publication number: 20220367396
    Abstract: A semiconductor device including: a first formation site and a second formation site for forming a first conductive bump and a second conductive bump; when a first environmental density corresponding to the first formation site is greater than a second environmental density corresponding to the second formation site, a cross sectional area of the second formation site is greater than a cross sectional area of the first formation site; wherein the first environmental density is determined by a number of formation sites around the first formation site in a predetermined range and the second environmental density is determined by a number of formation sites around the second formation site in the predetermined range; wherein a first area having the first environmental density forms an ellipse layout while a second area having the second environmental density forms a strip layout surrounding the ellipse layout.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 17, 2022
    Inventors: MING-HO TSAI, JYUN-HONG CHEN, CHUN-CHEN LIU, YU-NU HSU, PENG-REN CHEN, WEN-HAO CHENG, CHI-MING TSAI
  • Publication number: 20220328720
    Abstract: A method of manufacturing a light-emitting device, including: providing a substrate structure including a base portion and wherein the base portion includes a surface; performing a patterning step to form a plurality of protrusions, wherein the plurality of protrusions are arranged on the surface of the base portion; forming a buffer layer on the surface of the base portion by physical vapor deposition, wherein the buffer layer covers the protrusions; and forming III-V compound semiconductor layers on the buffer layer; wherein one of the plurality of protrusions has a height not greater than 1.5 ?m; and wherein the light-emitting device has a full width at half maximum (FWHM) of smaller than 250 arcsec in accordance with a (102) XRD rocking curve.
    Type: Application
    Filed: June 23, 2022
    Publication date: October 13, 2022
    Inventors: Peng Ren CHEN, Yu-Shan CHIU, Wen-Hsiang LIN, Shih-Wei WANG, Chen OU
  • Patent number: 11469198
    Abstract: A semiconductor device manufacturing method including: simultaneously forming a plurality of conductive bumps respectively on a plurality of formation sites by adjusting a forming factor in accordance with an environmental density associated with each formation site; wherein the plurality of conductive bumps including an inter-bump height uniformity smaller than a value, and the environmental density is determined by a number of neighboring formation sites around each formation site in a predetermined range.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: October 11, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ming-Ho Tsai, Jyun-Hong Chen, Chun-Chen Liu, Yu-Nu Hsu, Peng-Ren Chen, Wen-Hao Cheng, Chi-Ming Tsai
  • Patent number: 11398583
    Abstract: A light-emitting device, includes a substrate structure, including a base portion having a surface and a plurality of protrusions regularly formed on the base portion; a buffer layer covering the plurality of protrusions and the surface; and III-V compound semiconductor layers formed on the buffer layer; wherein one of the plurality of protrusions includes a first portion and a second portion formed on the first portion and the first portion is integrated with the base portion; and wherein the base portion includes a first material and the first portion includes the first material.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: July 26, 2022
    Assignee: EPISTAR CORPORATION
    Inventors: Peng Ren Chen, Yu-Shan Chiu, Wen-Hsiang Lin, Shih-Wei Wang, Chen Ou
  • Publication number: 20210342994
    Abstract: A method of analyzing a semiconductor wafer includes obtaining a graphic data system (GDS) file corresponding to the semiconductor wafer, using GDS information from the GDS file to provide coordinates of a layout feature of the semiconductor wafer to an electron microscope, using the electron microscope to capture a raw image from the semiconductor wafer based on the coordinates of the layout feature, and performing a measurement operation on the raw image.
    Type: Application
    Filed: July 16, 2021
    Publication date: November 4, 2021
    Inventors: Peng-Ren CHEN, Yi-An HUANG, Jyun-Hong CHEN, Wei-Chung HU, Wen-Hao CHENG, Shiang-Bau WANG, Yung-Jung CHANG
  • Patent number: 11094057
    Abstract: A method includes capturing a raw image from a semiconductor wafer, using graphic data system (GDS) information corresponding to the wafer to assign a measurement box in the raw image, performing a distance measurement on a feature of the raw image in the measurement box, and performing a manufacturing activity based on the distance measurement.
    Type: Grant
    Filed: August 3, 2020
    Date of Patent: August 17, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Peng-Ren Chen, Shiang-Bau Wang, Wen-Hao Cheng, Yung-Jung Chang, Wei-Chung Hu, Yi-An Huang, Jyun-Hong Chen
  • Publication number: 20200403120
    Abstract: A light-emitting device, includes a substrate structure, including a base portion having a surface and a plurality of protrusions regularly formed on the base portion; a buffer layer covering the plurality of protrusions and the surface; and III-V compound semiconductor layers formed on the buffer layer; wherein one of the plurality of protrusions includes a first portion and a second portion formed on the first portion and the first portion is integrated with the base portion; and wherein the base portion includes a first material and the first portion includes the first material.
    Type: Application
    Filed: September 2, 2020
    Publication date: December 24, 2020
    Inventors: Peng Ren CHEN, Yu-Shan CHIU, Wen-Hsiang LIN, Shih-Wei WANG, Chen OU
  • Publication number: 20200364844
    Abstract: A method includes capturing a raw image from a semiconductor wafer, using graphic data system (GDS) information corresponding to the wafer to assign a measurement box in the raw image, performing a distance measurement on a feature of the raw image in the measurement box, and performing a manufacturing activity based on the distance measurement.
    Type: Application
    Filed: August 3, 2020
    Publication date: November 19, 2020
    Inventors: Peng-Ren CHEN, Shiang-Bau WANG, Wen-Hao CHENG, Yung-Jung CHANG, Wei-Chung HU, Yi-An HUANG, Jyun-Hong CHEN
  • Patent number: 10784404
    Abstract: A light-emitting device, includes a substrate structure, including a base portion having a surface and a plurality of protrusions formed on the base portion; a buffer layer covering the plurality of protrusions and the surface; and III-V compound semiconductor layers formed on the buffer layer; wherein one of the plurality of protrusions has a height not greater than 1.5 ?m; wherein the light-emitting device has a full width at half maximum (FWHM) of smaller than 250 arcsec in accordance with a (102) XRD rocking curve.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: September 22, 2020
    Assignee: EPISTAR CORPORATION
    Inventors: Peng Ren Chen, Yu-Shan Chiu, Wen-Hsiang Lin, Shih-Wei Wang, Chen Ou
  • Patent number: 10762621
    Abstract: A method includes capturing a raw image from a semiconductor wafer, assigning a measurement box in the raw image, arranging a pair of indicators in the measurement box according to graphic data system (GDS) information of the semiconductor wafer, measuring a distance between the indicators, and performing a manufacturing activity based on the measured distance.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: September 1, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Peng-Ren Chen, Shiang-Bau Wang, Wen-Hao Cheng, Yung-Jung Chang, Wei-Chung Hu, Yi-An Huang, Jyun-Hong Chen
  • Publication number: 20200133959
    Abstract: Systematic fault localization systems and methods are provided which utilize computational GDS-assisted navigation to accelerate physical fault analysis to identify systematic fault locations and patterns. In some embodiments, a method includes detecting a plurality of electrical fault regions of a plurality of dies of a semiconductor wafer. Decomposed Graphic Database System (GDS) cross-layer clips are generated which are associated with the plurality of electrical fault regions. A plurality of cross-layer common patterns is identified based on the decomposed GDS cross-layer clips. Normalized differentials may be determined for each of the cross-layer common patterns, and locations of hotspots in each of the dies may be identified based on the determined normalized differentials.
    Type: Application
    Filed: July 31, 2019
    Publication date: April 30, 2020
    Inventors: Peng-Ren Chen, Wen-Hao Cheng, Jyun-Hong Chen, Chien-Hui Chen
  • Publication number: 20200020655
    Abstract: A semiconductor device manufacturing method including: simultaneously forming a plurality of conductive bumps respectively on a plurality of formation sites by adjusting a forming factor in accordance with an environmental density associated with each formation site; wherein the plurality of conductive bumps including an inter-bump height uniformity smaller than a value, and the environmental density is determined by a number of neighboring formation sites around each formation site in a predetermined range.
    Type: Application
    Filed: March 14, 2019
    Publication date: January 16, 2020
    Inventors: MING-HO TSAI, JYUN-HONG CHEN, CHUN-CHEN LIU, YU-NU HSU, PENG-REN CHEN, WEN-HAO CHENG, CHI-MING TSAI
  • Publication number: 20190334059
    Abstract: A light-emitting device, includes a substrate structure, including a base portion having a surface and a plurality of protrusions formed on the base portion; a buffer layer covering the plurality of protrusions and the surface; and III-V compound semiconductor layers formed on the buffer layer; wherein one of the plurality of protrusions has a height not greater than 1.5 ?m; wherein the light-emitting device has a full width at half maximum (FWHM) of smaller than 250 arcsec in accordance with a (102) XRD rocking curve.
    Type: Application
    Filed: April 29, 2019
    Publication date: October 31, 2019
    Inventors: Peng Ren CHEN, Yu-Shan CHIU, Wen-Hsiang LIN, Shih-Wei WANG, Chen OU
  • Publication number: 20190259140
    Abstract: A method includes capturing a raw image from a semiconductor wafer, assigning a measurement box in the raw image, arranging a pair of indicators in the measurement box according to graphic data system (GDS) information of the semiconductor wafer, measuring a distance between the indicators, and performing a manufacturing activity based on the measured distance.
    Type: Application
    Filed: May 1, 2019
    Publication date: August 22, 2019
    Inventors: Peng-Ren CHEN, Shiang-Bau WANG, Wen-Hao CHENG, Yung-Jung CHANG, Wei-Chung HU, Yi-An HUANG, Jyun-Hong CHEN
  • Patent number: 10304178
    Abstract: Methods and systems for diagnosing semiconductor wafer are provided. A target image is obtained according to graphic data system (GDS) information of a specific layout in the semiconductor wafer, wherein the target image includes a first contour having a first pattern corresponding to the specific layout. Image-based alignment is performed to capture a raw image from the semiconductor wafer according to the first contour. The semiconductor wafer is analyzed by measuring the raw image, so as to provide a diagnostic result.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: May 28, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANFACTURING COMPANY, LTD.
    Inventors: Peng-Ren Chen, Shiang-Bau Wang, Wen-Hao Cheng, Yung-Jung Chang, Wei-Chung Hu, Yi-An Huang, Jyun-Hong Chen
  • Publication number: 20190067516
    Abstract: The present disclosure provides a semiconductor device including a substrate, a first buffer structure and a semiconductor stack layer. The substrate includes a base part and a plurality of character parts connected to the base part. The first buffer structure is disposed on the base part and is separated from the plurality of character parts by at least one distance. The semiconductor stack layer is disposed on the first buffer structure and the plurality of character parts.
    Type: Application
    Filed: August 30, 2018
    Publication date: February 28, 2019
    Inventors: Chun-Hsiang TU, De-Shan KUO, Peng-Ren CHEN