Patents by Inventor Peng Shiu Chen

Peng Shiu Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070059910
    Abstract: A semiconductor structure and method for manufacturing the same is disclosed. The present invention relates to a semiconductor having a dielectric layer applied on a gate of a transistor, and a high dielectric-coefficient, and a manufacturing method of the semiconductor. Ti is formed on HfO2 to absorb oxygen from the dielectric layer to reduce its thickness, and even make it disappear. However, the TiO2 grown on the layer of Ti advances the growing of HfO2. Simultaneously, the dielectric constant of TiO2 is about 50. The TiO2 substantially enhances the dielectric constant for the dielectric layer. Ti absorbs the oxygen to reduce its thickness and increase the dielectric constant to reduce EOT. Moreover, TiO2 is formed and the dielectric constant is increased after heating. Accordingly, leakage is avoided in the TiO2. The present invention enhances the applications for high-k gate dielectrics with high electric constants, and continuously reduces the EOT.
    Type: Application
    Filed: March 15, 2006
    Publication date: March 15, 2007
    Inventors: Zing-Way Pei, Peng-Shiu Chen
  • Publication number: 20050082567
    Abstract: A structure of the relaxed SiGe epitaxial layer and a fabrication method comprises a Si substrate, a Si interfacial layer positioning on the substrate, a SiGe graded buffer layer positioning on the Si interfacial layer, and a uniform SiGe epitaxy layer positioning on the SiGe graded buffer layer. It uses a mesa structure and obtains a highly relaxed SiGe epitaxial layer with a low defect density of threading dislocations, a smooth surface. A strained Si can be formed on the strained relaxation layer. The strained Si, the strained Ge, the strained Si/Ge can apply to the high-speed planar electronic devices. By using a mesa structure, it can efficiently decrease the required growth time and cost in the conventional relaxed SiGe epitaxy layer.
    Type: Application
    Filed: May 19, 2004
    Publication date: April 21, 2005
    Applicant: Industrial Technology Research Institute
    Inventors: Peng Shiu Chen, Yang Tai Tseng, Chee Wee Liu