Patents by Inventor Peng Soon Lim
Peng Soon Lim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200279929Abstract: A semiconductor device includes a semiconductor substrate, a pair of source/drain regions, and a gate stack. The pair of source/drain regions is on the semiconductor substrate. The gate stack is laterally between the source/drain regions and includes a gate dielectric layer over the semiconductor fin, a metal element-containing layer over the gate dielectric layer, and a fill metal layer over the metal element-containing layer. The metal element-containing layer has a dopant, and a concentration of the dopant in an upper portion of the metal element-containing layer is higher than a concentration of the dopant in a bottom portion of the metal element-containing layer.Type: ApplicationFiled: May 15, 2020Publication date: September 3, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Cheng-Ming LIN, Peng-Soon LIM, Zi-Wei FANG
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Publication number: 20200251567Abstract: A method includes forming a trench over a substrate, wherein the trench is surrounded by gate spacers and an inter-layer dielectric layer, depositing a dielectric layer on a bottom and along sidewalls of the trench, depositing a metal layer over the dielectric layer, depositing a protection layer over the metal layer, wherein the protection layer has an uneven thickness, applying an etch-back process to the protection layer and the metal layer, wherein as a result of applying the etch-back process, a portion of the metal layer has been removed and at least a portion of the protection layer remains at the bottom of the trench and removing the protection layer from the trench.Type: ApplicationFiled: April 23, 2020Publication date: August 6, 2020Inventors: Peng-Soon Lim, Da-Yuan Lee, Kuang-Yuan Hsu
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Patent number: 10707131Abstract: A method includes forming in sequence a metallic capping layer and a dummy gate electrode layer over a semiconductor substrate; patterning the metallic capping layer and the dummy gate electrode layer to form a first stacked structure including a first portion of the metallic capping layer and a first portion of the dummy gate electrode layer; forming a plurality of first gate spacers on opposite sides of the first stacked structure; removing the first portion of the dummy gate electrode layer to expose the first portion of the metallic capping layer; and forming a first work function metal layer on the first portion of the metallic capping layer.Type: GrantFiled: August 14, 2018Date of Patent: July 7, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Peng-Soon Lim, Zi-Wei Fang
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Patent number: 10665685Abstract: A method includes forming a gate dielectric layer over a semiconductor substrate, forming a first metal element-containing layer over the gate dielectric layer, and thermal soaking the first metal element-containing layer in a first gas, such that a constituent of the first gas is diffused into the first metal element-containing layer.Type: GrantFiled: August 9, 2018Date of Patent: May 26, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Cheng-Ming Lin, Peng-Soon Lim, Zi-Wei Fang
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Patent number: 10651283Abstract: A method includes forming a trench over a substrate, wherein the trench is surrounded by gate spacers and an inter-layer dielectric layer, depositing a dielectric layer on a bottom and along sidewalls of the trench, depositing a metal layer over the dielectric layer, depositing a protection layer over the metal layer, wherein the protection layer has an uneven thickness, applying an etch-back process to the protection layer and the metal layer, wherein as a result of applying the etch-back process, a portion of the metal layer has been removed and at least a portion of the protection layer remains at the bottom of the trench and removing the protection layer from the trench.Type: GrantFiled: April 18, 2019Date of Patent: May 12, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Peng-Soon Lim, Da-Yuan Lee, Kuang-Yuan Hsu
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Publication number: 20200083351Abstract: A method includes forming a dummy gate stack, forming a dielectric layer, with the dummy gate stack located in the dielectric layer, removing the dummy gate stack to form a opening in the dielectric layer, forming a metal layer extending into the opening, and etching back the metal layer. The remaining portions of the metal layer in the opening have edges lower than a top surface of the dielectric layer. A conductive layer is selectively deposited in the opening. The conductive layer is over the metal layer, and the metal layer and the conductive layer in combination form a replacement gate.Type: ApplicationFiled: November 15, 2019Publication date: March 12, 2020Inventors: Peng-Soon Lim, Cheng-Lung Hung, Mao-Lin Huang, Weng Chang
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Publication number: 20200058553Abstract: A method includes forming in sequence a metallic capping layer and a dummy gate electrode layer over a semiconductor substrate; patterning the metallic capping layer and the dummy gate electrode layer to form a first stacked structure including a first portion of the metallic capping layer and a first portion of the dummy gate electrode layer; forming a plurality of first gate spacers on opposite sides of the first stacked structure; removing the first portion of the dummy gate electrode layer to expose the first portion of the metallic capping layer; and forming a first work function metal layer on the first portion of the metallic capping layer.Type: ApplicationFiled: August 14, 2018Publication date: February 20, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Peng-Soon LIM, Zi-Wei FANG
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Publication number: 20190245053Abstract: A method includes forming a trench over a substrate, wherein the trench is surrounded by gate spacers and an inter-layer dielectric layer, depositing a dielectric layer on a bottom and along sidewalls of the trench, depositing a metal layer over the dielectric layer, depositing a protection layer over the metal layer, wherein the protection layer has an uneven thickness, applying an etch-back process to the protection layer and the metal layer, wherein as a result of applying the etch-back process, a portion of the metal layer has been removed and at least a portion of the protection layer remains at the bottom of the trench and removing the protection layer from the trench.Type: ApplicationFiled: April 18, 2019Publication date: August 8, 2019Inventors: Peng-Soon Lim, Da-Yuan Lee, Kuang-Yuan Hsu
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Publication number: 20190165113Abstract: A method includes forming a gate dielectric layer over a semiconductor substrate, forming a first metal element-containing layer over the gate dielectric layer, and thermal soaking the first metal element-containing layer in a first gas, such that a constituent of the first gas is diffused into the first metal element-containing layer.Type: ApplicationFiled: August 9, 2018Publication date: May 30, 2019Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Cheng-Ming LIN, Peng-Soon LIM, Zi-Wei FANG
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Publication number: 20190165116Abstract: A semiconductor device includes a semiconductor substrate having a channel region. A gate dielectric layer is over the channel region of the semiconductor substrate. A work function metal layer is over the gate dielectric layer. The work function metal layer has a bottom portion, an upper portion, and a work function material. The bottom portion is between the gate dielectric layer and the upper portion. The bottom portion has a first concentration of the work function material, the upper portion has a second concentration of the work function material, and the first concentration is higher than the second concentration. A gate electrode is over the upper portion of the work function metal layer.Type: ApplicationFiled: July 10, 2018Publication date: May 30, 2019Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Peng-Soon LIM, Zi-Wei FANG, Cheng-Ming LIN
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Patent number: 10269912Abstract: A device comprises a metal gate structure over a substrate, wherein the metal gate structure comprises a first metal sidewall, a metal bottom layer, a first corner portion between the first metal sidewall and the metal bottom layer, wherein the first corner portion comprises a first step and a first ramp, a second metal sidewall and a second corner portion between the second metal sidewall and the metal bottom layer, wherein the second corner portion comprises a second step and a second ramp.Type: GrantFiled: April 3, 2018Date of Patent: April 23, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Peng-Soon Lim, Da-Yuan Lee, Kuang-Yuan Hsu
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Publication number: 20180226482Abstract: A device comprises a metal gate structure over a substrate, wherein the metal gate structure comprises a first metal sidewall, a metal bottom layer, a first corner portion between the first metal sidewall and the metal bottom layer, wherein the first corner portion comprises a first step and a first ramp, a second metal sidewall and a second corner portion between the second metal sidewall and the metal bottom layer, wherein the second corner portion comprises a second step and a second ramp.Type: ApplicationFiled: April 3, 2018Publication date: August 9, 2018Inventors: Peng-Soon Lim, Da-Yuan Lee, Kuang-Yuan Hsu
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Publication number: 20180175165Abstract: A method includes forming a dummy gate stack, forming a dielectric layer, with the dummy gate stack located in the dielectric layer, removing the dummy gate stack to form a opening in the dielectric layer, forming a metal layer extending into the opening, and etching back the metal layer. The remaining portions of the metal layer in the opening have edges lower than a top surface of the dielectric layer. A conductive layer is selectively deposited in the opening. The conductive layer is over the metal layer, and the metal layer and the conductive layer in combination form a replacement gate.Type: ApplicationFiled: June 13, 2017Publication date: June 21, 2018Inventors: Peng-Soon Lim, Cheng-Lung Hung, Mao-Lin Huang, Weng Chang
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Patent number: 9941373Abstract: A device comprises a metal gate structure over a substrate, wherein the metal gate structure comprises a first metal sidewall, a metal bottom layer, a first corner portion between the first metal sidewall and the metal bottom layer, wherein the first corner portion comprises a first step and a first ramp, a second metal sidewall and a second corner portion between the second metal sidewall and the metal bottom layer, wherein the second corner portion comprises a second step and a second ramp.Type: GrantFiled: August 31, 2016Date of Patent: April 10, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Peng-Soon Lim, Da-Yuan Lee, Kuang-Yuan Hsu
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Patent number: 9887090Abstract: A method comprises depositing a dielectric layer on sidewalls and a bottom of a trench of a gate structure, depositing a metal layer on the dielectric layer, depositing a protection layer on the metal layer, wherein an upper portion of a sidewall portion of the protection layer is thinner than a lower portion of the sidewall portion of the protection layer and etching back the metal wherein an upper portion of a first metal sidewall of the metal layer is thinner than a lower portion of the first metal sidewall and an upper portion of a second metal sidewall of the metal layer is thinner than a lower portion of the second metal sidewall.Type: GrantFiled: October 18, 2016Date of Patent: February 6, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Peng-Soon Lim, Tsai-Jung Ho
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Publication number: 20170040173Abstract: A method comprises depositing a dielectric layer on sidewalls and a bottom of a trench of a gate structure, depositing a metal layer on the dielectric layer, depositing a protection layer on the metal layer, wherein an upper portion of a sidewall portion of the protection layer is thinner than a lower portion of the sidewall portion of the protection layer and etching back the metal wherein an upper portion of a first metal sidewall of the metal layer is thinner than a lower portion of the first metal sidewall and an upper portion of a second metal sidewall of the metal layer is thinner than a lower portion of the second metal sidewall.Type: ApplicationFiled: October 18, 2016Publication date: February 9, 2017Inventors: Peng-Soon Lim, Tsai-Jung Ho
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Publication number: 20160372563Abstract: A device comprises a metal gate structure over a substrate, wherein the metal gate structure comprises a first metal sidewall, a metal bottom layer, a first corner portion between the first metal sidewall and the metal bottom layer, wherein the first corner portion comprises a first step and a first ramp, a second metal sidewall and a second corner portion between the second metal sidewall and the metal bottom layer, wherein the second corner portion comprises a second step and a second ramp.Type: ApplicationFiled: August 31, 2016Publication date: December 22, 2016Inventors: Peng-Soon Lim, Da-Yuan Lee, Kuang-Yuan Hsu
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Patent number: 9478623Abstract: A device comprises a metal gate structure in a trench and over a substrate, wherein the gate structure comprises a first metal sidewall in the trench, wherein the first metal sidewall becomes progressively thinner towards an upper portion of the first metal sidewall, a second metal sidewall in the trench, wherein the second metal sidewall becomes progressively thinner towards an upper portion of the second metal sidewall and a metal bottom layer on a bottom of the trench and between the first metal sidewall and the second metal sidewall.Type: GrantFiled: September 25, 2014Date of Patent: October 25, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Peng-Soon Lim, Tsai-Jung Ho
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Patent number: 9449832Abstract: A method comprises depositing a metal layer partially filling a trench of a gate structure, forming a protection layer on the metal layer, wherein a sidewall portion of the protection layer is thinner than a bottom portion of the protection layer, removing a portion of the metal layer and removing the bottom portion of the protection layer.Type: GrantFiled: June 1, 2015Date of Patent: September 20, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Peng-Soon Lim, Da-Yuan Lee, Kuang-Yuan Hsu
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Patent number: 9449828Abstract: An aspect of this description relates to a method that includes partially filling an opening in a dielectric material with a high-dielectric-constant material. The method also includes partially filling the opening with a first metal material over the high-dielectric-constant material. The method further includes filling the opening with a capping layer over the first metal material. The method additionally includes partially removing the first metal material and the capping layer in the opening using a wet etching process in a solution including one or more of H2O2, NH4OH, HCl, H2SO4 or diluted HF. The method also includes fully removing the remaining capping layer in the opening using a wet etching process in a solution includes one or more of NH4OH or diluted HF. The method further includes depositing a second metal material in the opening over the remaining first metal material.Type: GrantFiled: November 10, 2015Date of Patent: September 20, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Cheng-Hao Hou, Peng-Soon Lim, Da-Yuan Lee, Xiong-Fei Yu, Chun-Yuan Chou, Fan-Yi Hsu, Jian-Hao Chen, Kuang-Yuan Hsu