Abstract: A method for crystal pulling is provided. The method includes the following. The method includes performing an equal-diameter process. The equal-diameter process is performed as follows. From the first equal-diameter stage to the third equal-diameter stage, the crystal rotation rate is gradually increased after starting at a first initial crystal rotation rate, and then is kept at a constant rotation rate after gradually increasing the crystal rotation rate. The crucible rotation rate is gradually increased from a first initial crucible rotation rate to a maximum crucible rotation rate after starting at the first initial crucible rotation rate in the first equal-diameter stage, the crucible rotation rate is kept at the maximum crucible rotation rate in the second equal-diameter stage, and the crucible rotation rate is gradually decreased after the second equal-diameter stage. The method further includes a cooling process.

Abstract: The single crystal furnace charging system includes a control system configured to send a charging request, a material preparation system configured to receive the charging request and prepare materials based on the charging request, a feeding system configured to receive the charging request, obtain the materials, and compare an actual feeding amount with a preset feeding amount to obtain a difference between the actual feeding amount and the preset charging amount, in response to the difference being within a first preset threshold, charge a single crystal furnace. The single crystal furnace charging system further includes a calibration system configured to obtain a total charging weight, and obtain a difference between the total charging weight and a preset charging amount of the single crystal furnace, in response to the difference being within a second preset threshold, update a total charging amount to the total charging weight.

Abstract: Disclosed are a semiconductor structure and a preparation method thereof. The semiconductor structure includes a substrate, including a first region arranged at the center of the substrate and a second region arranged at the periphery of the first region; and a composite buffer layer arranged on the substrate, including a carbon-containing first buffer layer including at least one set of a first sub-buffer layer and a second sub-buffer layer stacked in layers; therein, a carbon concentration of the first sub-buffer layer arranged at the first region is higher than that arranged at the second region; and a carbon concentration of the second sub-buffer layer arranged at the first region is lower than that at arranged the second region. Therefore, uniformity of the carbon concentration of the composite buffer layer is improved to improve resistivity of the composite buffer layer, so as to increase breakdown voltage and improve device performance.

Abstract: The present application provides a substrate and a manufacturing method therefor. The substrate includes a silicon substrate and a protective layer, the silicon substrate includes a middle part and an edge part, and a thickness of the middle part is greater than a thickness of the edge part. The middle part has a to-be-grown surface, and a crystal orientation of the to-be-grown surface is different from a crystal orientation of surface of the edge part. The protective layer covers the edge part and is configured to prevent defects in the edge part from extending to the middle part during high-temperature processing.

Abstract: The present disclosure relates to an electronic display device for detecting and validating an object by optical sensing, comprising a display panel having light emitting pixels to display images, a top transparent surface formed over the display panel as an interface for being touched by a user for touch sensing operations, an optical sensor module located under the display panel or It integrated in the display panel comprising a sensor array of optical detector pixels configured for 1) receiving light reflected from the object on the surface of the display panel, and 2) generating image data according to the received light.

Abstract: A semiconductor structure and a manufacturing method thereof are provided in the present disclosure. The semiconductor structure includes a semiconductor substrate; a plurality of stacked structures and a plurality of isolation structures on the semiconductor substrate, wherein the stacked structures are spaced apart each other, and each of the isolation structures are located between adjacent stacked structures; each of the stacked structures comprises a nucleation layer and a first epitaxial layer from bottom to top; and a heterojunction structure on the plurality of stacked structures, wherein the heterojunction structure is distributed over an entire surface, and an air gap is formed between the heterojunction structure and each of the isolation structures.

Abstract: Methods, apparatuses, and systems associated with personal protective equipment are provided. An example mask may include an exterior layer, one or more mask straps coupled to the exterior layer, and a filter layer. An example method for manufacturing a protective garment may include providing a front segment, providing a back segment, and connecting the front segment and the back segment by at least forming a front raglan seam.

Abstract: Disclosed is a method of manufacturing a semiconductor structure, including: providing a silicon substrate (10), epitaxially growing a functional layer (11) on an upper surface of the silicon substrate, where a material of the functional layer includes a group-III-nitride-based material; implanting ions into an interface between the upper surface of silicon substrate and the functional layer to introduce defects to the interface; or implanting, before epitaxially growing the functional layer, ions to the upper surface of the silicon substrate to introduce defects to the interface.

Abstract: The present application provides a method of manufacturing a semiconductor structure. The manufacturing method includes following steps: at step S1: forming a first epitaxial structure above a substrate, where the first epitaxial structure is doped with a doping element; at step S2: forming a sacrificial layer above the first epitaxial structure; at step S3: etching the sacrificial layer; at step S4: growing an insertion layer above the first epitaxial structure when the etching of the sacrificial layer is completed; and at step S5: growing a second epitaxial structure above the insertion layer; before proceeding to step S4, repeating step S2 and step S3, until a concentration of the doping element in the first epitaxial structure is lower than a predetermined threshold.

Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a semiconductor substrate, a back barrier layer, a channel layer and an etch stop layer arranged from bottom to up; and a P-type semiconductor layer located in a source region and a drain region on the etch stop layer. Due to the setting of the etch stop layer, when the P-type semiconductor layer in the gate region is removed by etching, etching can be stopped at the etch stop layer, and the etching depth can be accurately controlled without causing etching damage to the channel layer. The carrier mobility of holes in the channel in the semiconductor structure is improved, and yield and performance of the device are improved.

Abstract: Disclosed is a preparation method for a semiconductor structure. The semiconductor structure includes: a substrate; an epitaxial layer and an epitaxial structure that are stacked on the substrate in sequence. The epitaxial layer is doped with a doping element. In the forming process, a sacrificial layer is formed on the epitaxial layer, and the sacrificial layer is repeatedly etched, such that a concentration of the doping element in the epitaxial layer is lower than a preset value. In this application, the sacrificial layer is formed on the epitaxial layer, and the sacrificial layer is repeatedly etched, such that the concentration of the doping element in the epitaxial layer is lower than the preset value, so as to prevent the doping element in the epitaxial layer from being precipitated upward into an upper-layer structure, ensure the mobility of electrons in a channel layer, and improve the performance of a device.

Abstract: Disclosed are a Li+ doped metal halide scintillation crystal with a zero-dimensional perovskite structure, a preparation method and use thereof. The scintillation crystal has a chemical formula of Cs3-xCu2I5:xLi, where x is in a range of 0.003 to 0.3. The method for preparing the scintillation crystal comprises the steps of: weighting and fully mixing a CuI powder, a CsI powder and a LiI powder in a molar ratio of 2:(3-x):x in an inert atmosphere to obtain a mixed powder, and growing into the scintillation crystal from the mixed powder by Bridgman Stockbarger method. After excited, the scintillation crystal could emit a broadband blue light in a range of 350-550 nm, with an intensity much higher than that of the original pure component crystal. The existence of Li+ further expands the application of the scintillation crystals from X/?-ray detection to neutron detection.

Abstract: The present disclosure relates to a method for fabrication of an optical sensor for use in an image recognition device, e.g. a biometric imaging device, such as a fingerprint detector, for use in under-display applications. The presently disclosed method provides a cost-efficient fabrication process, preferably employing nanoimprint lithography, for realizing an optical sensor with improved light transmittance in a compact and cost-efficient structure. In particular the presently disclosed image recognition device can be placed under a display panel of an electronic device, such as a smartphone.

Abstract: In general, this invention discloses methods for extracting and analyzing coatings from implanted and excised animal tissue medical devices; wherein the coating comprises at least one biodegradable polymer and at least one or more therapeutic ingredients. The present invention describes optimal conditions for extraction and isolation of biodegradable polymers and therapeutics in medical devices or complex pharmaceutical agent formulations prior and after implanting or injecting into animal tissues. Particularly this work relates to accurate isolation and quantification of ppm amounts of polymer and/or therapeutics without biological interferences. The use of GPC/SEC systems equipped with light scattering detectors enables “absolute” or “true” molecular weight determination. All of these improvements allow for accurate determination of the degradation profile of the polymer/therapeutic component independent of polymer standards used in conventional GPC/SEC.

Abstract: Disclosed is a graphite plate to solve a problem of poor performance uniformity of an epitaxial wafer obtained by using a graphite plate for epitaxial growth. The graphite plate includes a graphite plate body, the graphite plate body includes a carrying recess, and at least part of the inner wall of the carrying recess is covered with a heat insulation material.

Abstract: Disclosed is a graphite plate to solve a problem of poor performance uniformity of an epitaxial wafer obtained during carrying on epitaxial growth of material using the graphite plate. A graphite plate includes: a graphite plate body, includes a carrying recess and a recess located on one side of the carrying recess away from a central point of the graphite plate body; and a stopper, which is embedded in the recess in a matching manner, and the stopper protrudes from the bottom surface of the carrying recess to form a limiting structure.

Abstract: A non-metallic layer stranded optical cable with a reversal point capable of being positioned and a detection method thereof, which solves the problems of determining a reversal point of a cable core and performing an operation of drawing out an optical fiber from the optical cable. The present invention relates to a non-metallic layer stranded optical cable, and the key points of the technical solution thereof includes a cable core and a metal film provided at each reversal point of the cable core, and an outer sheath is provided on the cable core.

Abstract: The present disclosure relates to an optical sensor for use in an image recognition device, such as a fingerprint detector. The presently disclosed optical sensor has improved light transmittance in a compact and cost-efficient structure. In particular the presently disclosed optical sensor can be placed under a display panel of an electronic device, such as a smartphone. One embodiment relates to an optical sensor system for placement under a display panel for detecting/imaging light returned from a fingerprint on top of the display panel, the optical sensor comprising a microlens structure having a front side with an array of light focusing elements and an opaque back side with an array of optically transparent apertures aligned with the focusing elements, and a sensor array of optical detectors facing the back side of the microlens structure.

Abstract: The present disclosure relates to an optical sensor for use in an image recognition device, such as a fingerprint detector. The presently disclosed optical sensor has improved light transmittance in a compact and cost-efficient structure. In particular the presently disclosed optical sensor can be placed under a display panel of an electronic device, such as a smartphone. One embodiment relates to an optical sensor system for placement under a display panel for detecting/imaging light returned from a fingerprint on top of the display panel, the optical sensor comprising a microlens structure having a front side with an array of light focusing elements and an opaque back side with an array of optically transparent apertures aligned with the focusing elements, and a sensor array of optical detectors facing the back side of the microlens structure.

Abstract: The present application discloses a semiconductor structure and a preparation method. The semiconductor structure includes a heterojunction, including at least two sets of channel layers and barrier layers stacked sequentially; a first p-type semiconductor, disposed in a gate region of the heterojunction and extended to a bottom of the heterojunction; and a second p-type semiconductor, disposed on the gate region of the heterojunction. By providing a heterojunction including at least two sets of channel layers and barrier layers stacked sequentially, multilayer 2DEG is realized by using multilayer channel layers and barrier layers to increase the concentration of 2DEG, thereby reducing the resistance. Since a first p-type semiconductor is disposed in a gate region of the heterojunction, the p-type semiconductor materials in the first p-type semiconductor are used to deplete the 2DEG to realize normally-off and increase the threshold voltage.