Patents by Inventor Peng Xiang
Peng Xiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250227981Abstract: The present disclosure provides a HEMT device and a manufacturing method thereof. The HEMT device includes: a substrate, a heterojunction structure, a P-type semiconductor layer, a first stress layer and/or a second stress layer, a gate, a source and a drain, where the first stress layer is located on the opposite sidewalls of the P-type semiconductor layer, and is configured to apply compressive stress to the P-type semiconductor layer in the direction parallel to the plane where the substrate is located, and to apply tensile stress to the P-type semiconductor layer in the direction perpendicular to the plane where the substrate is located. The second stress layer is located on the top wall of the P-type semiconductor layer, and is configured to apply compressive stress to the P-type semiconductor layer in the direction parallel to the plane where the substrate is located.Type: ApplicationFiled: November 5, 2021Publication date: July 10, 2025Applicant: ENKRIS SEMICONDUCTOR, INC.Inventors: Peng XIANG, Kai CHENG
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Patent number: 12315096Abstract: The embodiments of the present disclosure provide an interaction method and apparatus, device and medium, wherein the interaction method includes: in response to a trigger operation on a target interaction anchor on a video page, obtaining an image to be processed and a material of a target item associated with the target interaction anchor; and generating a target image based on the material of the target item and the image to be processed.Type: GrantFiled: August 1, 2024Date of Patent: May 27, 2025Assignee: Beijing Youzhuju Network Technology Co., Ltd.Inventors: Zhe Li, Hao Liu, Kequan Fan, Longfei Mu, Peng Xiang, Haiyang Cao
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Patent number: 12298213Abstract: In general, this invention discloses methods for extracting and analyzing coatings from implanted and excised animal tissue medical devices; wherein the coating comprises at least one biodegradable polymer and at least one or more therapeutic ingredients. The present invention describes optimal conditions for extraction and isolation of biodegradable polymers and therapeutics in medical devices or complex pharmaceutical agent formulations prior and after implanting or injecting into animal tissues. Particularly this work relates to accurate isolation and quantification of ppm amounts of polymer and/or therapeutics without biological interferences. The use of GPC/SEC systems equipped with light scattering detectors enables “absolute” or “true” molecular weight determination. All of these improvements allow for accurate determination of the degradation profile of the polymer/therapeutic component independent of polymer standards used in conventional GPC/SEC.Type: GrantFiled: June 26, 2020Date of Patent: May 13, 2025Inventors: Amer Ebied, Eric D. Landry, Peng Xiang, Solmaz Karamdoust
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Patent number: 12276041Abstract: A method for crystal pulling is provided. The method includes the following. The method includes performing an equal-diameter process. The equal-diameter process is performed as follows. From the first equal-diameter stage to the third equal-diameter stage, the crystal rotation rate is gradually increased after starting at a first initial crystal rotation rate, and then is kept at a constant rotation rate after gradually increasing the crystal rotation rate. The crucible rotation rate is gradually increased from a first initial crucible rotation rate to a maximum crucible rotation rate after starting at the first initial crucible rotation rate in the first equal-diameter stage, the crucible rotation rate is kept at the maximum crucible rotation rate in the second equal-diameter stage, and the crucible rotation rate is gradually decreased after the second equal-diameter stage. The method further includes a cooling process.Type: GrantFiled: December 30, 2022Date of Patent: April 15, 2025Assignees: SICHUAN JINKO SOLAR CO., LTD., JINKO SOLAR CO., LTD.Inventors: Chunsheng Su, Yuang Yang, Peng Xiang, Bo Xiong
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Patent number: 12276040Abstract: The single crystal furnace charging system includes a control system configured to send a charging request, a material preparation system configured to receive the charging request and prepare materials based on the charging request, a feeding system configured to receive the charging request, obtain the materials, and compare an actual feeding amount with a preset feeding amount to obtain a difference between the actual feeding amount and the preset charging amount, in response to the difference being within a first preset threshold, charge a single crystal furnace. The single crystal furnace charging system further includes a calibration system configured to obtain a total charging weight, and obtain a difference between the total charging weight and a preset charging amount of the single crystal furnace, in response to the difference being within a second preset threshold, update a total charging amount to the total charging weight.Type: GrantFiled: December 21, 2022Date of Patent: April 15, 2025Assignees: JINKO SOLAR CO., LTD., SICHUAN JINKO SOLAR CO., LTD.Inventors: Ziyang Ou, Yin Tang, Bo Xiong, Peng Xiang
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Publication number: 20250109520Abstract: A manufacturing method for a single-crystal silicon rod and a single-crystal furnace. The single-crystal silicon rod is pulled through a single-crystal furnace, and a crucible of the single-crystal furnace has a depth ranging from 680 mm to 800 mm. The manufacturing method for a single-crystal silicon rod includes: initially charging a silicon material to the crucible, wherein a contact area between the silicon material in the crucible and the crucible is a, a contact area between a liquid level of the silicon material in the crucible and the outside is b, and 1.2?a/b?3.7.Type: ApplicationFiled: December 22, 2023Publication date: April 3, 2025Inventors: Peng XIANG, Ziyang OU, Xufan LI, Yonghui LI, Yuang YANG
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Patent number: 12183576Abstract: Disclosed is a preparation method for a semiconductor structure. The semiconductor structure includes: a substrate; an epitaxial layer and an epitaxial structure that are stacked on the substrate in sequence. The epitaxial layer is doped with a doping element. In the forming process, a sacrificial layer is formed on the epitaxial layer, and the sacrificial layer is repeatedly etched, such that a concentration of the doping element in the epitaxial layer is lower than a preset value. In this application, the sacrificial layer is formed on the epitaxial layer, and the sacrificial layer is repeatedly etched, such that the concentration of the doping element in the epitaxial layer is lower than the preset value, so as to prevent the doping element in the epitaxial layer from being precipitated upward into an upper-layer structure, ensure the mobility of electrons in a channel layer, and improve the performance of a device.Type: GrantFiled: October 19, 2022Date of Patent: December 31, 2024Assignee: ENKRIS SEMICONDUCTOR, INC.Inventors: Peng Xiang, Kai Cheng
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Publication number: 20240386683Abstract: The embodiments of the present disclosure provide an interaction method and apparatus, device and medium, wherein the interaction method includes: in response to a trigger operation on a target interaction anchor on a video page, obtaining an image to be processed and a material of a target item associated with the target interaction anchor; and generating a target image based on the material of the target item and the image to be processed.Type: ApplicationFiled: August 1, 2024Publication date: November 21, 2024Inventors: Zhe LI, Hao LIU, Kequan FAN, Longfei MU, Peng XIANG, Haiyang CAO
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Patent number: 12136668Abstract: A semiconductor structure includes a heterojunction, including at least two sets of channel layers and barrier layers stacked sequentially; a first p-type semiconductor, disposed in a gate region of the heterojunction and extended to a bottom of the heterojunction; and a second p-type semiconductor, disposed on the gate region of the heterojunction. By providing a heterojunction including at least two sets of channel layers and barrier layers stacked sequentially, multilayer 2DEG is realized by using multilayer channel layers and barrier layers to increase the concentration of 2DEG, thereby reducing the resistance. Since a first p-type semiconductor is disposed in a gate region of the heterojunction, the p-type semiconductor materials in the first p-type semiconductor are used to deplete the 2DEG to realize normally-off and increase the threshold voltage.Type: GrantFiled: May 10, 2021Date of Patent: November 5, 2024Assignee: ENKRIS SEMICONDUCTOR, INC.Inventors: Kai Cheng, Peng Xiang, Yu Zhu
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Patent number: 12136559Abstract: Disclosed is a graphite plate to solve a problem of poor performance uniformity of an epitaxial wafer obtained during carrying on epitaxial growth of material using the graphite plate. A graphite plate includes: a graphite plate body, includes a carrying recess and a recess located on one side of the carrying recess away from a central point of the graphite plate body; and a stopper, which is embedded in the recess in a matching manner, and the stopper protrudes from the bottom surface of the carrying recess to form a limiting structure.Type: GrantFiled: January 25, 2022Date of Patent: November 5, 2024Assignee: ENKRIS SEMICONDUCTOR, INC.Inventor: Peng Xiang
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Publication number: 20240304712Abstract: A semiconductor structure includes a first semiconductor layer, a second semiconductor layer, and a gate. The second semiconductor layer is disposed on the first semiconductor layer. The first semiconductor layer and the second semiconductor layer form a heterostructure. The gate is disposed on the gate region of the second semiconductor layer. In the gate region, multiple spacing layers arranged at intervals are disposed between the second semiconductor layer and the first semiconductor layer along the extension direction of the gate. Each of the spacing layers forms a current path across the length of a channel.Type: ApplicationFiled: October 30, 2023Publication date: September 12, 2024Inventors: Guoqiao TAO, Peng XIANG, Kai LIU
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Publication number: 20240218483Abstract: The present application discloses a lithium extraction method for an alkaline solution, in which a lithium adsorption material is used in an alkaline environment. Lithium ions in the alkaline solution are adsorbed, the lithium adsorption material is replaced with an alkaline high-lithium low-impurity solution, and then an acid solution is used for desorption, so that a high-lithium salt solution having higher lithium content can be obtained. Lithium concentration can reach 5 g/L or more, and the high-lithium salt solution can enter a bipolar membrane system for electrolysis, thereby preparing an alkaline high-lithium low-impurity solution and an acid solution for replacement and desorption of the lithium adsorption material. In the method provided by the present application, lithium in an alkaline solution is adsorbed by resin, and the lithium is preliminarily separated from sodium and potassium.Type: ApplicationFiled: August 9, 2022Publication date: July 4, 2024Inventors: Suidang LI, Xiaokang KOU, Fumin GUO, Jia YU, Wenjin GAO, Lili FAN, Kaile CHU, Weina BIAN, Yao WANG, Peng XIANG, Qiong LIU
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Publication number: 20240125005Abstract: A method for crystal pulling is provided. The method includes the following. The method includes performing an equal-diameter process. The equal-diameter process is performed as follows. From the first equal-diameter stage to the third equal-diameter stage, the crystal rotation rate is gradually increased after starting at a first initial crystal rotation rate, and then is kept at a constant rotation rate after gradually increasing the crystal rotation rate. The crucible rotation rate is gradually increased from a first initial crucible rotation rate to a maximum crucible rotation rate after starting at the first initial crucible rotation rate in the first equal-diameter stage, the crucible rotation rate is kept at the maximum crucible rotation rate in the second equal-diameter stage, and the crucible rotation rate is gradually decreased after the second equal-diameter stage. The method further includes a cooling process.Type: ApplicationFiled: December 30, 2022Publication date: April 18, 2024Inventors: Chunsheng SU, Yuang YANG, Peng XIANG, Bo XIONG
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Publication number: 20240060207Abstract: The single crystal furnace charging system includes a control system configured to send a charging request, a material preparation system configured to receive the charging request and prepare materials based on the charging request, a feeding system configured to receive the charging request, obtain the materials, and compare an actual feeding amount with a preset feeding amount to obtain a difference between the actual feeding amount and the preset charging amount, in response to the difference being within a first preset threshold, charge a single crystal furnace. The single crystal furnace charging system further includes a calibration system configured to obtain a total charging weight, and obtain a difference between the total charging weight and a preset charging amount of the single crystal furnace, in response to the difference being within a second preset threshold, update a total charging amount to the total charging weight.Type: ApplicationFiled: December 21, 2022Publication date: February 22, 2024Inventors: Ziyang OU, Yin TANG, Bo XIONG, PENG XIANG
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Publication number: 20240063257Abstract: Disclosed are a semiconductor structure and a preparation method thereof. The semiconductor structure includes a substrate, including a first region arranged at the center of the substrate and a second region arranged at the periphery of the first region; and a composite buffer layer arranged on the substrate, including a carbon-containing first buffer layer including at least one set of a first sub-buffer layer and a second sub-buffer layer stacked in layers; therein, a carbon concentration of the first sub-buffer layer arranged at the first region is higher than that arranged at the second region; and a carbon concentration of the second sub-buffer layer arranged at the first region is lower than that at arranged the second region. Therefore, uniformity of the carbon concentration of the composite buffer layer is improved to improve resistivity of the composite buffer layer, so as to increase breakdown voltage and improve device performance.Type: ApplicationFiled: August 2, 2023Publication date: February 22, 2024Applicant: ENKRIS SEMICONDUCTOR, INC.Inventors: Peng XIANG, Kai CHENG
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Publication number: 20230402282Abstract: The present application provides a substrate and a manufacturing method therefor. The substrate includes a silicon substrate and a protective layer, the silicon substrate includes a middle part and an edge part, and a thickness of the middle part is greater than a thickness of the edge part. The middle part has a to-be-grown surface, and a crystal orientation of the to-be-grown surface is different from a crystal orientation of surface of the edge part. The protective layer covers the edge part and is configured to prevent defects in the edge part from extending to the middle part during high-temperature processing.Type: ApplicationFiled: November 13, 2020Publication date: December 14, 2023Applicant: ENKRIS SEMICONDUCTOR, INC.Inventors: Kai Cheng, Peng Xiang
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Publication number: 20230334898Abstract: The present disclosure relates to an electronic display device for detecting and validating an object by optical sensing, comprising a display panel having light emitting pixels to display images, a top transparent surface formed over the display panel as an interface for being touched by a user for touch sensing operations, an optical sensor module located under the display panel or It integrated in the display panel comprising a sensor array of optical detector pixels configured for 1) receiving light reflected from the object on the surface of the display panel, and 2) generating image data according to the received light.Type: ApplicationFiled: June 24, 2021Publication date: October 19, 2023Inventors: Weiqi Xue, Peng Xiang, Jørgen Korsgaard Jensen
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Publication number: 20230238446Abstract: A semiconductor structure and a manufacturing method thereof are provided in the present disclosure. The semiconductor structure includes a semiconductor substrate; a plurality of stacked structures and a plurality of isolation structures on the semiconductor substrate, wherein the stacked structures are spaced apart each other, and each of the isolation structures are located between adjacent stacked structures; each of the stacked structures comprises a nucleation layer and a first epitaxial layer from bottom to top; and a heterojunction structure on the plurality of stacked structures, wherein the heterojunction structure is distributed over an entire surface, and an air gap is formed between the heterojunction structure and each of the isolation structures.Type: ApplicationFiled: November 6, 2020Publication date: July 27, 2023Applicant: ENKRIS SEMICONDUCTOR, INC.Inventors: Kai Cheng, Peng Xiang
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Publication number: 20230172291Abstract: Methods, apparatuses, and systems associated with personal protective equipment are provided. An example mask may include an exterior layer, one or more mask straps coupled to the exterior layer, and a filter layer. An example method for manufacturing a protective garment may include providing a front segment, providing a back segment, and connecting the front segment and the back segment by at least forming a front raglan seam.Type: ApplicationFiled: May 15, 2020Publication date: June 8, 2023Inventors: Rui LUO, Jing XU, Xiaobai RUAN, Menglong GAO, Hongbing XIANG, Yiwei ZHANG, Peng XIANG, Yuyan WANG, Bingzhong XIA
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Publication number: 20230178631Abstract: Disclosed is a method of manufacturing a semiconductor structure, including: providing a silicon substrate (10), epitaxially growing a functional layer (11) on an upper surface of the silicon substrate, where a material of the functional layer includes a group-III-nitride-based material; implanting ions into an interface between the upper surface of silicon substrate and the functional layer to introduce defects to the interface; or implanting, before epitaxially growing the functional layer, ions to the upper surface of the silicon substrate to introduce defects to the interface.Type: ApplicationFiled: September 23, 2020Publication date: June 8, 2023Applicant: ENKRIS SEMICONDUCTOR, INC.Inventors: Kai Cheng, Peng Xiang