Patents by Inventor Peng ZUO
Peng ZUO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12007906Abstract: A method includes configuring a memory for storing a kernel page table and a user page table to low-order address space, and reserving high-order address space, obtaining register configuration information of a kernel page table of a second operating system from the second operating system, and configuring a register of the high-order address space of a first operating system based on the register configuration information of the kernel page table of the second operating system such that the high-order address space is enabled to directly access a kernel resource of the second operating system.Type: GrantFiled: May 20, 2022Date of Patent: June 11, 2024Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Peng Zuo, Xiaoqiang Du, Yong Chen
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Publication number: 20240175324Abstract: The disclosure discloses a penetrating cushion damping device comprising a penetrator, and belongs to the field of in-situ penetrating exploration of extraterrestrial celestial bodies. A magnetic conductor encloses the non-penetrating end of the penetrator, a drag plate connected to the penetrator is provided at the lower end face of the magnetic conductor, and a magnetic source structure for generating magnetic force on the magnetic conductor is provided in the non-penetrating end of the penetrator. The disclosure utilizes the penetrating cushion anti-drag mode with the drag plate and the electromagnetic structure, which is self-adaptive to the flight penetration speed and compact in structure, reduces the jump probability, and further reduces the cushion resistance after the speed is reduced.Type: ApplicationFiled: December 21, 2022Publication date: May 30, 2024Inventors: XINJIAN WANG, YI ZUO, CHENG QIAN, ANLIN JIANG, LISHENG DENG, YUNYUN GUO, XIANDONG NIE, JIN LIU, PENG LU, YUEHAI CHEN, YUBIN YANG
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Publication number: 20240178956Abstract: Provided are a channel configuration method and terminal, a storage medium and an electronic device. The method includes: determining that multiple physical channels overlap in a time domain; and determining a physical channel for carrying information or data in the multiple physical channels, wherein the determined physical channel is a Physical Uplink Control Channel (PUCCH), and determining a physical channel comprises: among the multiple physical channels, processing a physical channel with earlier first symbol before a physical channel with later first symbol, and when two or more physical channels in the multiple physical channels have the same first symbol, processing a physical channel with a larger number of symbols before a physical channel with a smaller number of symbols.Type: ApplicationFiled: February 5, 2024Publication date: May 30, 2024Inventors: Wei GOU, Peng HAO, Zhisong ZUO, Ting FU
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Publication number: 20240158994Abstract: An adjustment method of moisture content and dense state for a hydrogel improved subgrade based on weather-resistance during an in-service period, including: step 1: carrying out surface cleaning and compaction of ground; step 2: preparing hydrogel improved subgrade raw material; step 3: paving the prepared material on the surface to form first-layer improved subgrade; and step 4: paving plain soil subgrade onto the first-layer. The method combines the water absorption and release function of the modified resin and the characteristic of the gel state thereof, to pave the improved subgrade in layers, which can absorb water and slightly expand when the water content in the subgrade is increased to a certain threshold value, and a strength and compactness protective layer can also be formed at the connection sections of the ground and the subgrade, and the subgrade and the pavement, to prevent the pot-cover effect from occurring.Type: ApplicationFiled: October 31, 2022Publication date: May 16, 2024Applicants: SHANDONG JIAOTONG UNIVERSITY, SHANDONG UNIVERSITY, CHONGQING UNIVERSITY, JINAN JINYUE HIGHWAY ENGINEERING CO., LTD.Inventors: Xinzhuang CUI, Jin LI, Qing JIN, Shen ZUO, Dalu XIONG, Peng JIANG, Xiaoning ZHANG, Yefeng DU, Kai YUAN, Chongsheng XIN
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Patent number: 11985088Abstract: Methods, systems, and devices for generating sequences for reference signals in mobile communication technology are described. An exemplary method for wireless communication includes transmitting data, which is modulated using a pi/2-binary phase shift keying (BPSK) modulation, and a reference signal using a plurality of subcarriers, where the reference signal comprises a sequence from a subset of sequences that contains 30 sequences, each with a predetermined length, and where the subset of sequences include at least a first number of fixed sequences and a second number of selected sequences. The method further enables constructing the sequences, which have low peak-to-average power ratio (PAPR) properties, for sequence lengths N=6, 12, 18, 24 and 30.Type: GrantFiled: April 30, 2021Date of Patent: May 14, 2024Assignee: ZTE CorporationInventors: Chunli Liang, Chuangxin Jiang, Zhisong Zuo, Shuqiang Xia, Peng Hao
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Patent number: 11974257Abstract: Provided are a time domain resource allocation method and apparatus. The method includes the following operations. A terminal acquires at least one of first information including search space configuration information, control resource set (CORESET) configuration information, and a bandwidth part type. A PDSCH time domain resource allocation table is subsequently determined according to the first information and a multiplexing pattern between a synchronization signal/physical broadcast channel block (SSB) and a CORESET.Type: GrantFiled: September 19, 2019Date of Patent: April 30, 2024Assignee: ZTE CORPORATIONInventors: Xing Liu, Peng Hao, Xianghui Han, Zhisong Zuo
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Patent number: 11956167Abstract: Provided are a channel configuration method and terminal, a storage medium and an electronic device. The method includes: determining that multiple physical channels overlap in a time domain; and determining a physical channel for carrying information or data in the multiple physical channels, wherein the determined physical channel is a Physical Uplink Control Channel (PUCCH), and determining a physical channel comprises: among the multiple physical channels, processing a physical channel with earlier first symbol before a physical channel with later first symbol, and when two or more physical channels in the multiple physical channels have the same first symbol, processing a physical channel with a larger number of symbols before a physical channel with a smaller number of symbols.Type: GrantFiled: May 22, 2023Date of Patent: April 9, 2024Assignee: ZTE CorporationInventors: Wei Gou, Peng Hao, Zhisong Zuo, Ting Fu
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Publication number: 20220276968Abstract: A method includes configuring a memory for storing a kernel page table and a user page table to low-order address space, and reserving high-order address space, obtaining register configuration information of a kernel page table of a second operating system from the second operating system, and configuring a register of the high-order address space of a first operating system based on the register configuration information of the kernel page table of the second operating system such that the high-order address space is enabled to directly access a kernel resource of the second operating system.Type: ApplicationFiled: May 20, 2022Publication date: September 1, 2022Inventors: Peng Zuo, Xiaoqiang Du, Yong Chen
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Patent number: 11228418Abstract: A example receiver includes analog circuitry configured to equalize and amplify an input signal and provide an analog signal as output; clock data recovery (CDR) circuitry configured to recover data clocks and edge clocks from the analog signal; a plurality of eye height optimization circuits, each of the plurality of eye height optimization circuits configured to, based on a respective data pattern of a plurality of data patterns, sample the analog signal based on the data clocks and the edge clocks, feed back first information to the analog circuitry for adjusting the eye amplitude, and feed back second information to the CDR circuitry for adjusting the data clocks; and an eye width optimization circuit configured to receive data and edge samples from the plurality of eye height optimization circuits, feed back third information to the CDR circuitry to adjust the edge clocks, and feed back fourth information to the analog circuitry to adjust the equalization.Type: GrantFiled: November 30, 2018Date of Patent: January 18, 2022Assignee: International Business Machines CorporationInventors: Xiao Di Xing, Zhen Peng Zuo, Yang Xiao, Xu Guang Sun
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Patent number: 11120185Abstract: The computer processor identifies a first shared set of input ports that are common to a first hardware model and a second hardware model and a second shared set of input ports that are common to a first reference model and a second reference model. The computer processor selects logic of the first hardware model and logic of the second hardware model that are each traceable to the first shared set of input ports and selects logic of the first reference model and logic of the second reference model that are each traceable to the second shared set of input ports. The computer processor determines that the logic of the second hardware model and the logic of the second reference model have verified logic by determining that the logic of the first hardware model is equivalent to the logic of the second hardware model and the logic of the first reference model is equivalent to the logic of the second reference model.Type: GrantFiled: November 29, 2018Date of Patent: September 14, 2021Assignee: International Business Machines CorporationInventors: Yan Heng Lu, Chen Qian, Zhen Peng Zuo, Heng Liu, Peng Fei Gou, Yang Fan Liu
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Publication number: 20210266311Abstract: Provided in the present application are a blockchain and DNSSEC-based user authentication method, a system, a device, and a medium, the method comprising: when an encrypted connection over Internet need to be performed between a server and a client, authenticating, by the server, the identity of the client by means of a blockchain-based authentication mechanism, and authenticating, by the client, the identity of the server by means of a DNSSEC-based mechanism. According to the blockchain and DNSSEC-based user authentication method provided in the present application, mutual authentication for an encrypted connection process over Internet is achieved by means of blockchain and DNSSEC-based validation mechanisms without relying on CA authentication. Thus, there are no problems of CA single point of failure or multi-CA mutual trust risk. In addition, the blockchain and DNSSEC-based user authentication method according to the present application is relatively convenient to be implemented.Type: ApplicationFiled: February 28, 2019Publication date: August 26, 2021Inventors: Yu ZENG, Yuedong ZHANG, Peng ZUO, Meng YUAN, Haikuo ZHANG, Weiping YANG
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Patent number: 11048630Abstract: A symmetrical multi-processing (SMP) node, a distributed SMP (DSMP) system comprising a plurality of SMP nodes, and a method implemented in the SMP node are disclosed. The SMP node comprises: a plurality of processors, a memory coupled to the plurality of processors, and a memory coherent proxy coupled to the plurality of processors through a coherent accelerator interface. The memory coherent proxy is configured to manage statuses of cache lines in the memory.Type: GrantFiled: November 27, 2018Date of Patent: June 29, 2021Assignee: International Business Machines CorporationInventors: Zhen Peng Zuo, Peng Fei Gou, Yang Fan Liu, Yang Liu, Hua Xin Yao
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Patent number: 10769331Abstract: An apparatus for verification includes a processing module, a data collection module, an engine selection module and an engine execution module. The processing module processes a netlist using a plurality of engines. The netlist includes components and nodes of an integrated circuit design. Each engine includes an algorithm for verification of the integrated circuit design. The data collection module stores, for each engine, execution results for the engine for a plurality of netlists, the results stored in a history buffer. The engine selection module, for a current netlist, calculates using execution results in the history buffer which engine of the plurality of engines has a highest predicted performance and selects the engine with the highest predicted performance. The engine execution module executes the current netlist using the selected engine to produce execution results, reports the execution results and stores the execution results in the history buffer.Type: GrantFiled: July 12, 2018Date of Patent: September 8, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Peng Fei Gou, Heng Liu, Yang Fan Liu, Yan Heng Lu, Chen Qian, Zhen Peng Zuo
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Patent number: 10699044Abstract: An apparatus for model splitting includes an extraction module that extracts netlist parameters from a static netlist. The netlist parameters include node parameters of each node of the static netlist. The node parameters include node connection information and execution cycle information. The nodes of the static netlist include nodes of an integrated circuit design from an input to an output. A split node module analyzes, using the netlist parameters, each node in a cycle and determines if each node is a potential split node, which is a node with a projected sub-proof execution time less than a time limit. A split chain module determines if a split chain exists. The split chain includes a connection between potential split nodes from the input to the output at each execution cycle. A reporting module reports nodes of a split chain in response to determining that a split chain exists.Type: GrantFiled: July 13, 2018Date of Patent: June 30, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Chen Qian, Heng Liu, Peng Fei Gou, Yang Fan Liu, Yan Heng Lu, Zhen Peng Zuo
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Publication number: 20200175128Abstract: The computer processor identifies a first shared set of input ports that are common to a first hardware model and a second hardware model and a second shared set of input ports that are common to a first reference model and a second reference model. The computer processor selects logic of the first hardware model and logic of the second hardware modelt that are each traceable to the first shared set of input ports and selects logic of the first reference model and logic of the second reference model that are each traceable to the second shared set of input ports. The computer processor determines that the logic of the second hardware model and the logic of the second reference model have verified logic by determining that the logic of the first hardware model is equivalent to the logic of the second hardware model and the logic of the first reference model is equivalent to the logic of the second reference model.Type: ApplicationFiled: November 29, 2018Publication date: June 4, 2020Inventors: Yan Heng LU, Chen QIAN, Zhen Peng ZUO, Heng LIU, Peng Fei GOU, Yang Fan LIU
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Publication number: 20200175299Abstract: A example receiver includes analog circuitry configured to equalize and amplify an input signal and provide an analog signal as output; clock data recovery (CDR) circuitry configured to recover data clocks and edge clocks from the analog signal; a plurality of eye height optimization circuits, each of the plurality of eye height optimization circuits configured to, based on a respective data pattern of a plurality of data patterns, sample the analog signal based on the data clocks and the edge clocks, feed back first information to the analog circuitry for adjusting the eye amplitude, and feed back second information to the CDR circuitry for adjusting the data clocks; and an eye width optimization circuit configured to receive data and edge samples from the plurality of eye height optimization circuits, feed back third information to the CDR circuitry to adjust the edge clocks, and feed back fourth information to the analog circuitry to adjust the equalization.Type: ApplicationFiled: November 30, 2018Publication date: June 4, 2020Inventors: Xiao Di XING, Zhen Peng ZUO, Yang XIAO, Xu Guang SUN
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Publication number: 20200167283Abstract: A symmetrical multi-processing (SMP) node, a distributed SMP (DSMP) system comprising a plurality of SMP nodes, and a method implemented in the SMP node are disclosed. The SMP node comprises: a plurality of processors, a memory coupled to the plurality of processors, and a memory coherent proxy coupled to the plurality of processors through a coherent accelerator interface. The memory coherent proxy is configured to manage statuses of cache lines in the memory.Type: ApplicationFiled: November 27, 2018Publication date: May 28, 2020Inventors: Zhen Peng Zuo, Peng Fei Gou, Yang Fan Liu, Yang Liu, Hua Xin Yao
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Patent number: 10585841Abstract: Techniques and systems for performing calibration. A method includes: creating a common calibration pool for performing a calibration operation for two or more communication links, wherein the calibration operation is common to the two or more communication links; and performing a calibration on each of the two or more communication links using the common calibration pool by receiving a calibration request associated with the common calibration operation via a link calibration interface, wherein the calibration request is from at least one of the two or more communication links, upon determining the calibration agent is available to handle the calibration request, retrieving a calibration engine from at least one of the plurality of calibration clusters corresponding to the calibration operation, retrieving a calibration engine from at least one of the plurality of calibration clusters corresponding to the calibration operation, and performing the common calibration based on the retrieving.Type: GrantFiled: July 24, 2018Date of Patent: March 10, 2020Assignee: International Business Machines CorporationInventors: Xu Guang Sun, Yang Xiao, Xiao Di Xing, Zhen Peng Zuo
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Publication number: 20200034328Abstract: Techniques and systems for performing calibration. A method includes: creating a common calibration pool for performing a calibration operation for two or more communication links, wherein the calibration operation is common to the two or more communication links; and performing a calibration on each of the two or more communication links using the common calibration pool by receiving a calibration request associated with the common calibration operation via a link calibration interface, wherein the calibration request is from at least one of the two or more communication links, upon determining the calibration agent is available to handle the calibration request, retrieving a calibration engine from at least one of the plurality of calibration clusters corresponding to the calibration operation, retrieving a calibration engine from at least one of the plurality of calibration clusters corresponding to the calibration operation, and performing the common calibration based on the retrieving.Type: ApplicationFiled: July 24, 2018Publication date: January 30, 2020Inventors: Xu Guang SUN, Yang XIAO, Xiao Di XING, Zhen Peng ZUO
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Publication number: 20200019652Abstract: An apparatus for model splitting includes an extraction module that extracts netlist parameters from a static netlist. The netlist parameters include node parameters of each node of the static netlist. The node parameters include node connection information and execution cycle information. The nodes of the static netlist include nodes of an integrated circuit design from an input to an output. A split node module analyzes, using the netlist parameters, each node in a cycle and determines if each node is a potential split node, which is a node with a projected sub-proof execution time less than a time limit. A split chain module determines if a split chain exists. The split chain includes a connection between potential split nodes from the input to the output at each execution cycle. A reporting module reports nodes of a split chain in response to determining that a split chain exists.Type: ApplicationFiled: July 13, 2018Publication date: January 16, 2020Inventors: CHEN QIAN, HENG LIU, PENG FEI GOU, YANG FAN LIU, YAN HENG LU, ZHEN PENG ZUO