Abstract: The disclosure provides an integrity measurement method, including two environments: a TEE and a non-TEE. The TEE includes a first trusted zone and a TEE management module. The first trusted zone is isolated from each component in the non-TEE and another trusted zone in the TEE. In other words, in a case of not being authorized, each component in the non-TEE and a component in the another trusted zone in the TEE do not have an access permission on a component in the first trusted zone. In embodiments of this application, a measurement module configured to perform integrity measurement is located in the first trusted zone, and performs an integrity measurement procedure by using a lightweight TEE management module as a trusted base.

Abstract: A method includes configuring a memory for storing a kernel page table and a user page table to low-order address space, and reserving high-order address space, obtaining register configuration information of a kernel page table of a second operating system from the second operating system, and configuring a register of the high-order address space of a first operating system based on the register configuration information of the kernel page table of the second operating system such that the high-order address space is enabled to directly access a kernel resource of the second operating system.

Abstract: A method includes configuring a memory for storing a kernel page table and a user page table to low-order address space, and reserving high-order address space, obtaining register configuration information of a kernel page table of a second operating system from the second operating system, and configuring a register of the high-order address space of a first operating system based on the register configuration information of the kernel page table of the second operating system such that the high-order address space is enabled to directly access a kernel resource of the second operating system.

Abstract: A example receiver includes analog circuitry configured to equalize and amplify an input signal and provide an analog signal as output; clock data recovery (CDR) circuitry configured to recover data clocks and edge clocks from the analog signal; a plurality of eye height optimization circuits, each of the plurality of eye height optimization circuits configured to, based on a respective data pattern of a plurality of data patterns, sample the analog signal based on the data clocks and the edge clocks, feed back first information to the analog circuitry for adjusting the eye amplitude, and feed back second information to the CDR circuitry for adjusting the data clocks; and an eye width optimization circuit configured to receive data and edge samples from the plurality of eye height optimization circuits, feed back third information to the CDR circuitry to adjust the edge clocks, and feed back fourth information to the analog circuitry to adjust the equalization.

Abstract: The computer processor identifies a first shared set of input ports that are common to a first hardware model and a second hardware model and a second shared set of input ports that are common to a first reference model and a second reference model. The computer processor selects logic of the first hardware model and logic of the second hardware model that are each traceable to the first shared set of input ports and selects logic of the first reference model and logic of the second reference model that are each traceable to the second shared set of input ports. The computer processor determines that the logic of the second hardware model and the logic of the second reference model have verified logic by determining that the logic of the first hardware model is equivalent to the logic of the second hardware model and the logic of the first reference model is equivalent to the logic of the second reference model.

Abstract: Provided in the present application are a blockchain and DNSSEC-based user authentication method, a system, a device, and a medium, the method comprising: when an encrypted connection over Internet need to be performed between a server and a client, authenticating, by the server, the identity of the client by means of a blockchain-based authentication mechanism, and authenticating, by the client, the identity of the server by means of a DNSSEC-based mechanism. According to the blockchain and DNSSEC-based user authentication method provided in the present application, mutual authentication for an encrypted connection process over Internet is achieved by means of blockchain and DNSSEC-based validation mechanisms without relying on CA authentication. Thus, there are no problems of CA single point of failure or multi-CA mutual trust risk. In addition, the blockchain and DNSSEC-based user authentication method according to the present application is relatively convenient to be implemented.

Abstract: A symmetrical multi-processing (SMP) node, a distributed SMP (DSMP) system comprising a plurality of SMP nodes, and a method implemented in the SMP node are disclosed. The SMP node comprises: a plurality of processors, a memory coupled to the plurality of processors, and a memory coherent proxy coupled to the plurality of processors through a coherent accelerator interface. The memory coherent proxy is configured to manage statuses of cache lines in the memory.

Abstract: An apparatus for verification includes a processing module, a data collection module, an engine selection module and an engine execution module. The processing module processes a netlist using a plurality of engines. The netlist includes components and nodes of an integrated circuit design. Each engine includes an algorithm for verification of the integrated circuit design. The data collection module stores, for each engine, execution results for the engine for a plurality of netlists, the results stored in a history buffer. The engine selection module, for a current netlist, calculates using execution results in the history buffer which engine of the plurality of engines has a highest predicted performance and selects the engine with the highest predicted performance. The engine execution module executes the current netlist using the selected engine to produce execution results, reports the execution results and stores the execution results in the history buffer.

Abstract: An apparatus for model splitting includes an extraction module that extracts netlist parameters from a static netlist. The netlist parameters include node parameters of each node of the static netlist. The node parameters include node connection information and execution cycle information. The nodes of the static netlist include nodes of an integrated circuit design from an input to an output. A split node module analyzes, using the netlist parameters, each node in a cycle and determines if each node is a potential split node, which is a node with a projected sub-proof execution time less than a time limit. A split chain module determines if a split chain exists. The split chain includes a connection between potential split nodes from the input to the output at each execution cycle. A reporting module reports nodes of a split chain in response to determining that a split chain exists.

Abstract: The computer processor identifies a first shared set of input ports that are common to a first hardware model and a second hardware model and a second shared set of input ports that are common to a first reference model and a second reference model. The computer processor selects logic of the first hardware model and logic of the second hardware modelt that are each traceable to the first shared set of input ports and selects logic of the first reference model and logic of the second reference model that are each traceable to the second shared set of input ports. The computer processor determines that the logic of the second hardware model and the logic of the second reference model have verified logic by determining that the logic of the first hardware model is equivalent to the logic of the second hardware model and the logic of the first reference model is equivalent to the logic of the second reference model.

Abstract: A example receiver includes analog circuitry configured to equalize and amplify an input signal and provide an analog signal as output; clock data recovery (CDR) circuitry configured to recover data clocks and edge clocks from the analog signal; a plurality of eye height optimization circuits, each of the plurality of eye height optimization circuits configured to, based on a respective data pattern of a plurality of data patterns, sample the analog signal based on the data clocks and the edge clocks, feed back first information to the analog circuitry for adjusting the eye amplitude, and feed back second information to the CDR circuitry for adjusting the data clocks; and an eye width optimization circuit configured to receive data and edge samples from the plurality of eye height optimization circuits, feed back third information to the CDR circuitry to adjust the edge clocks, and feed back fourth information to the analog circuitry to adjust the equalization.

Abstract: A symmetrical multi-processing (SMP) node, a distributed SMP (DSMP) system comprising a plurality of SMP nodes, and a method implemented in the SMP node are disclosed. The SMP node comprises: a plurality of processors, a memory coupled to the plurality of processors, and a memory coherent proxy coupled to the plurality of processors through a coherent accelerator interface. The memory coherent proxy is configured to manage statuses of cache lines in the memory.

Abstract: Techniques and systems for performing calibration. A method includes: creating a common calibration pool for performing a calibration operation for two or more communication links, wherein the calibration operation is common to the two or more communication links; and performing a calibration on each of the two or more communication links using the common calibration pool by receiving a calibration request associated with the common calibration operation via a link calibration interface, wherein the calibration request is from at least one of the two or more communication links, upon determining the calibration agent is available to handle the calibration request, retrieving a calibration engine from at least one of the plurality of calibration clusters corresponding to the calibration operation, retrieving a calibration engine from at least one of the plurality of calibration clusters corresponding to the calibration operation, and performing the common calibration based on the retrieving.

Abstract: Techniques and systems for performing calibration. A method includes: creating a common calibration pool for performing a calibration operation for two or more communication links, wherein the calibration operation is common to the two or more communication links; and performing a calibration on each of the two or more communication links using the common calibration pool by receiving a calibration request associated with the common calibration operation via a link calibration interface, wherein the calibration request is from at least one of the two or more communication links, upon determining the calibration agent is available to handle the calibration request, retrieving a calibration engine from at least one of the plurality of calibration clusters corresponding to the calibration operation, retrieving a calibration engine from at least one of the plurality of calibration clusters corresponding to the calibration operation, and performing the common calibration based on the retrieving.

Abstract: An apparatus for model splitting includes an extraction module that extracts netlist parameters from a static netlist. The netlist parameters include node parameters of each node of the static netlist. The node parameters include node connection information and execution cycle information. The nodes of the static netlist include nodes of an integrated circuit design from an input to an output. A split node module analyzes, using the netlist parameters, each node in a cycle and determines if each node is a potential split node, which is a node with a projected sub-proof execution time less than a time limit. A split chain module determines if a split chain exists. The split chain includes a connection between potential split nodes from the input to the output at each execution cycle. A reporting module reports nodes of a split chain in response to determining that a split chain exists.

Abstract: An apparatus for verification includes a processing module, a data collection module, an engine selection module and an engine execution module. The processing module processes a netlist using a plurality of engines. The netlist includes components and nodes of an integrated circuit design. Each engine includes an algorithm for verification of the integrated circuit design. The data collection module stores, for each engine, execution results for the engine for a plurality of netlists, the results stored in a history buffer. The engine selection module, for a current netlist, calculates using execution results in the history buffer which engine of the plurality of engines has a highest predicted performance and selects the engine with the highest predicted performance. The engine execution module executes the current netlist using the selected engine to produce execution results, reports the execution results and stores the execution results in the history buffer.

Abstract: An ultrasonic humidifier includes a tank having a water level and a floater having a tubular structure with a bottom rim and a top rim. The tubular structure has a frusto-conical shape and is vertically and co-axially disposed within the floater. The tubular structure having a widest diameter end disposed on the bottom rim and a narrower diameter end disposed at the top rim. This humidifier also has an air-supply arrangement that eliminates water damage to the fan during spillage.