Abstract: The present disclosure relates to the technical field of semiconductors, and provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate; a bit line located on the substrate; and a support layer located on the substrate, wherein the support layer includes a first support segment and a second support segment, the first support segment and the second support segment are both connected to the bit line, and the bit line is located between the first support segment and the second support segment.

Abstract: The present disclosure provides a manufacturing method of a semiconductor structure, including: an insulating layer includes a first dielectric layer and a second dielectric layer, a protective layer covers an upper surface of the second dielectric layer and a bottom and sidewalls of the first trench; removing part of the protective layer to expose at least part of a surface of the second dielectric layer; removing the second dielectric layer by a first wet etching process, the first wet etching process has a first etch selectivity of a material of the second dielectric layer to that of the first dielectric layer; and removing the protective layer by a second wet etching process, the second wet etching process has a second etch selectivity of a material of the protective layer to that of the first dielectric layer, and the second etch selectivity is greater than the first etch selectivity.

Abstract: An embodiment of the application provides a method for forming a semiconductor structure. The semiconductor structure includes a first region and a second region. The method includes the following steps: providing a base, an insulating layer, and a mask layer that are stacked in sequence, where the first region has at least one trench penetrating the mask layer and the insulating layer, and the mask layer has an upper surface in the second region higher than that in the first region; forming a first protection layer, where an upper surface and a sidewall of the mask layer in the first region are covered with the first protection layer; after the first protection layer is formed, removing the mask layer in the second region; subsequent to removal of the mask layer in the second region, removing the first protection layer; and removing the mask layer in the first region.

Abstract: A method for manufacturing a mask structure includes: patterning a sacrificial layer and a second dielectric layer, so as to form pattern structures each including a first pattern and a second pattern, and a width of a lower portion of the pattern structures is less than a width of a upper portion of the pattern structures; forming an initial mask pattern on sidewalls of each of the plurality of pattern structures; filling a first filling layer between adjacent initial mask patterns located on the sidewalls of different pattern structures; removing the second patterns and the initial mask pattern located on sidewalls of each of the plurality of second patterns; removing the first filling layer and the first patterns, so as to form first mask patterns; and forming second mask patterns on the first mask patterns.

Abstract: An array structure of capacitors are provided. The array structure of capacitors includes a substrate and a first connection pad, a second connection pad, a first capacitive structure and a second capacitive structure that are disposed on the substrate. The first capacitive structure is disposed outside the second capacitive structure and adjacent to an edge of the substrate. The bottom surface of the first capacitive structure towards the substrate and the top surface of the first connection pad are disposed at intervals.

Abstract: A mask structure, a semiconductor structure and methods for manufacturing the same are disclosed. The method for manufacturing the mask structure includes: forming a pattern transfer layer, a first etching stop layer, a first sacrificial layer and a first hard mask layer sequentially stacked from bottom to top; patterning the first sacrificial layer and the first hard mask layer, to obtain a first sacrificial pattern, the first sacrificial pattern exposing the first etching stop layer; forming a first initial mask pattern on side walls of the first sacrificial pattern; removing the first sacrificial pattern; removing, based on the first initial mask pattern, a part of the first etching stop layer of which a top surface being exposed; removing the first initial mask pattern, and using the remaining part of the first etching stop layer on the upper surface of the pattern transfer layer as a first mask pattern.

Abstract: A method for forming a pattern can include the following operations. A substrate is provided, on the surface of which a patterned photoresist layer is formed. Based on the photoresist layer, isolation sidewalls are formed, in which each isolation sidewall includes a first sidewall close to the photoresist layer and a second sidewall away from the photoresist layer. Core material layers are formed between two adjacent isolation sidewalls. The second sidewalls are removed to form the pattern composed of the first sidewalls and the core material layers.

Abstract: An embodiment of the disclosure provides a method for manufacturing a semiconductor structure, including: providing a substrate, where the substrate has a peripheral region and an array region; stacking and forming an insulating layer and a mask layer with a mask pattern on the substrate; etching the insulating layer with the mask layer as a mask to form a contact hole penetrating the insulating layer at the array region; reserving the mask layer; in a direction perpendicular to a surface of the substrate, providing a thickness difference between the mask layer of the peripheral region and the mask layer of the array region; forming a first material layer; forming a second material layer; etching a part of the mask layer with the second material layer as the mask; and removing the remaining second material layer, the remaining mask layer and the first material layer on the remaining mask layer.

Abstract: A method for manufacturing a memory and a memory is provided. The method for manufacturing a memory includes: providing a substrate; stacking an electrode support structure, a protective layer and a first mask layer in sequence on the substrate; patterning the first mask layer on an array region, and etching the protective layer, the electrode support structure and the substrate by using the patterned first mask layer as a mask, to form capacitor holes penetrating the protective layer and the electrode support structure and extending into the substrate; removing the first mask layer; and forming a first electrode layer on side walls and bottom walls of the capacitor holes, a top surface of the first electrode layer being flush with a top surface of the electrode support structure.

Abstract: A method for manufacturing a memory includes: providing a substrate, capacitor contact pads being formed in the substrate; forming a laminated structure on the substrate, the laminated structure including a first laminated structure formed on the substrate and a second laminated structure formed on the first laminated structure; forming first through holes in the second laminated structure; forming a protective layer on side walls of the first through holes, the protective layer in the first through holes enclosing second through holes; and etching the first laminated structure along the second through holes to form third through holes, the third through holes exposing the capacitor contact pads.

Abstract: Embodiment relates to a method for fabricating a semiconductor structure. The method includes: forming a first pattern on the first region and forming a second pattern on the second region, wherein the first pattern includes a plurality of first sub-patterns, a first gap is provided between adjacent two of the plurality of first sub-patterns, a width of the first gap is a first pitch, and wherein the second pattern includes a plurality of second sub-patterns, a second gap is provided between adjacent two of the plurality of second sub-patterns, a width of the second gap is a second pitch, and the second pitch is greater than the first pitch; forming a first mask layer on a sidewall of the first pattern, and forming a second mask layer on a sidewall of the second pattern; and removing the first pattern and the second pattern.

Abstract: A method for forming a capacitor array structure includes the following operations. A base is formed, which includes a substrate, a stack structure located on the substrate and a mask layer located on the stack structure in which an etching window that penetrates the mask layer in a direction perpendicular to the substrate is provided. The stack structure is etched along the etching window to form a capacitor hole that penetrates the stack structure along the direction perpendicular to the substrate. A conductive layer that fills up the capacitor hole and the etching window and covers a top surface of the mask layer is formed. The conductive layer and the mask layer at a top surface of the stack structure are removed, and the conductive layer remaining in the capacitor hole forms a lower electrode.

Abstract: The present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure, and relates to the technical field of semiconductors. The manufacturing method includes: providing a base, wherein the base is provided with an active region; forming a gate layer on the base; forming isolation structures on a periphery of the gate layer, wherein in a direction away from the gate layer, each of the isolation structures at least includes a hollow portion and an isolation portion; forming an insulating structure on top surfaces of the isolation structures; forming contact plugs, wherein the contact plugs penetrate the insulating structure; an end of each of the contact plugs close to the base is electrically connected to the active region; each of the contact plugs is located on a side of each of the isolation structures away from the gate layer.

Abstract: The present application provides a method for preparing a semiconductor structure and a semiconductor structure, relating to the technical field of semiconductors. The method for preparing a semiconductor structure includes: providing a base; forming a support layer having capacitor holes and electric contact structures; forming a first dielectric layer in the capacitor holes, the first dielectric layer surrounding first intermediate holes; forming a first electrode layer in the first intermediate holes, the first electrode layer filling the first intermediate holes; removing part of the support layer to form second intermediate holes; forming a second dielectric layer in the second intermediate holes, the first dielectric layer and the second dielectric layer forming a dielectric layer; and, forming a second electrode layer on the dielectric layer.

Abstract: The present application relates to a mask structure, a semiconductor structure and methods for manufacturing the same. The method for manufacturing a mask structure includes: dividing an overall structure into two regions, and developing the array region and the periphery region with a negative photoresist.

Abstract: A method for manufacturing a semiconductor structure includes: a substrate is provided, in which the substrate is provided with a peripheral area and an array area; an insulation layer is formed on the substrate; a first mask layer with a first mask pattern is formed on the insulation layer; the insulation layer is etched by taking the first mask layer as a mask, to form a contact hole in the array area; a first electrode layer is formed; a second mask layer with a second mask pattern is formed, in which the second mask layer is arranged on the first electrode layer; and the first electrode layer and the first mask layer are etched by taking the second mask layer as a mask until the insulation layer in the array area is exposed, in which a remaining portion of the first electrode layer forms a lower electrode layer.

Abstract: Embodiments of the present disclosure provide a patterning method and a semiconductor structure. The method includes: providing a substrate, wherein the substrate includes adjacent storage regions and peripheral circuit regions; forming, on the substrate, a pattern transfer layer, the pattern transfer layer having a plurality of first hard masks, wherein the first hard masks extend along a first direction and are spaced apart from each other; forming a barrier layer on the pattern transfer layer; forming, on the barrier layer, a plurality of second hard masks, the plurality of second hard masks extending along a second direction, wherein the second hard masks are spaced apart from each other, and the second hard masks are located in the storage regions and second hard masks close to the peripheral circuit regions have structural defects.

Abstract: The present disclosure discloses a capacitor structure and its formation method and a memory. The method includes: providing a substrate; forming an electrode support structure on the substrate in a stacking fashion, wherein the electrode support structure includes at least a first support layer on its top, a capacitor hole is formed at intervals within the electrode support structure and extends upwards in a direction perpendicular to a surface of the substrate; forming, within the capacitor hole, an electrode post and an electrode layer extending from the electrode post to the upper surface of the first support layer; removing the electrode layer; removing the first support layer; forming a dielectric layer on the top of the electrode support structure, wherein the dielectric layer covers the top of the electrode post, and an outer peripheral wall of the top of the electrode post is connected with the dielectric layer.

Abstract: A method for manufacturing a semiconductor structure includes: providing a base; forming multiple discrete first mask layers on the base; forming multiple sidewall layers, in which each sidewall layer is configured to encircle one of the first mask layers, and each sidewall layer is connected to closest sidewall layers, the side walls, away from the first mask layers, of multiple connected sidewall layers define initial first vias and each of the initial first vias is provided with chamfers; removing the first mask layers, and each sidewall layer defines a second via; after removing the first mask layers, forming repair layers which are located on the side walls, away from the second vias, of the sidewall layers and fill the chamfers of the initial first vias to form first vias; and etching the base along the first vias and the second vias to form capacitor holes on the base.

Abstract: A method for manufacturing a memory includes: providing a substrate, capacitor contact pads being formed in the substrate; forming a laminated structure on the substrate, the laminated structure including a first laminated structure formed on the substrate and a second laminated structure formed on the first laminated structure; forming first through holes in the second laminated structure; forming a protective layer on side walls of the first through holes, the protective layer in the first through holes enclosing second through holes; and etching the first laminated structure along the second through holes to form third through holes, the third through holes exposing the capacitor contact pads.