Abstract: Computing architecture comprises an off-chip memory, an on-chip cache unit, a prefetching unit, a global scheduler, a transmitting unit, a pre-recombination network, a post-recombination network, a main computing array, a write-back cache unit, a data dependence controller and an auxiliary computing array. The architecture reads data tiles into an on-chip cache in a prefetching mode, and performs computing according to the data tiles; in the computing process of the tiles, a tile exchange network is adopted to recombine a data structure, and a data dependence module is arranged to process a data dependence relationship possibly existing between different tiles. According to the computing architecture, the data utilization rate can be increased, the data processing flexibility is improved, and therefore Cache Miss is reduced, and the memory bandwidth pressure is reduced.

Abstract: Computing architecture comprises an off-chip memory, an on-chip cache unit, a prefetching unit, a global scheduler, a transmitting unit, a pre-recombination network, a post-recombination network, a main computing array, a write-back cache unit, a data dependence controller and an auxiliary computing array. The architecture reads data tiles into an on-chip cache in a prefetching mode, and performs computing according to the data tiles; in the computing process of the tiles, a tile exchange network is adopted to recombine a data structure, and a data dependence module is arranged to process a data dependence relationship possibly existing between different tiles. According to the computing architecture, the data utilization rate can be increased, the data processing flexibility is improved, and therefore Cache Miss is reduced, and the memory bandwidth pressure is reduced.

Abstract: A multifunctional data reorganization network includes a binary switching unit and a recursive shuffle network (RSN), wherein both the binary switching unit and the recursive shuffle network can enable bidirectional transmission of data, and the data reorganization network completes data reorganization by controlling the transmission direction of a signal in the network. The network may serve as a data transfer path between a storage unit and a computation unit to perform multiple data reorganization functions while transferring data, thereby enabling flexible data structure adjustment of non-regular data, and thus improving data transfer efficiency and computational efficiency of non-regular computation.

Abstract: A parallel computing system is provided, including input ports, a first switching network, a computing array, a second switching network and output ports. The first switching network is receiving input data from the input ports, sequencing the input data according to different computing modes of the computing array and outputting sequenced input data; the computing array is performing parallel computation on the sequenced input data and outputting intermediate data; and the second switching network is sequencing the intermediate data according to different output modes and outputting sequenced intermediate data through the output ports. The present disclosure applies the switching networks to the parallel computing system and performs any required sequencing on the input or output data according to the different computing modes and output modes to complete various arithmetic operations through the computing array after the input data are input into the computing array.

Abstract: A parallel computing system is provided, including input ports, a first switching network, a computing array, a second switching network and output ports. The first switching network is receiving input data from the input ports, sequencing the input data according to different computing modes of the computing array and outputting sequenced input data; the computing array is performing parallel computation on the sequenced input data and outputting intermediate data; and the second switching network is sequencing the intermediate data according to different output modes and outputting sequenced intermediate data through the output ports. The present disclosure applies the switching networks to the parallel computing system and performs any required sequencing on the input or output data according to the different computing modes and output modes to complete various arithmetic operations through the computing array after the input data are input into the computing array.

Abstract: A parallel synchronous scaling engine for multi-view 3D display and a method thereof are provided, wherein selection and combination calculation are provided to an interpolation pixel window, then interpolation calculation is provided to a combined interpolation pixel window of a combined view field, calculation results are directly displayed on a display terminal. That is to say, interpolation is originally provided before stereoscopic pixel rearrangement, which is now improved, in such a manner that screening and combination of pixel points is provided before interpolation calculation. According to the present invention, computation and memory resource is greatly saved. The method is suitable to be implemented by hardware, for satisfying various numbers of viewpoints and interpolation algorithm, and being compatible with multi-view 3D display with the integrated and floating-point pixel arrangement, wherein the computation resource does not need to be increased with increasing of the viewpoints.

Abstract: A parallel synchronous scaling engine for multi-view 3D display and a method thereof are provided, wherein, selection and combination calculation are provided to an interpolation pixel window, then interpolation calculation is provided to a combined interpolation pixel window of a combined view field, calculation results are directly displayed on a display terminal. That is to say, interpolation is originally provided before stereoscopic pixel rearrangement, which is now improved, in such a manner that screening and combination of pixel points is provided before interpolation calculation. According to the present invention, computation and memory resource is greatly saved. The method is suitable to be implemented by hardware, for satisfying various numbers of viewpoints and interpolation algorithm, and being compatible with multi-view 3D display with the integrated and floating-point pixel arrangement, wherein the computation resource does not need to be increased with increasing of the viewpoints.