Abstract: Apparatuses, systems, and methods for a wireless device to perform methods for determining resources for scheduling side-link communications. The resources may be semi-persistent and/or dynamic resources. A user equipment device (UE) may determine a resource map for use in scheduling semi-persistent resources for side-link communications with at least one wireless node. The UE may transmit a resource map request message indicating preferred resource blocks, where each resource block may be defined by a time and a frequency. The UE may receive a confirmation message that may include a report regarding a set of resource blocks. The set of resource blocks may be from the preferred resource blocks included in the resource map request message. The UE may determine, based, at least in part, on the confirmation message, resource blocks to be used for the side-link communications and initiate the side-link communications using the determined resource blocks.

Abstract: The present application discloses a method for manufacturing a NAND flash, comprising: step 1, sequentially form a floating gate dielectric layer and a first polysilicon layer; step 2, sequentially forming an inter-gate dielectric layer and a second polysilicon layer, wherein a first doping concentration of the second polysilicon layer is less than a target doping concentration; step 3, forming a pattern transfer mask layer; step 4, patterning the pattern transfer mask layer; step 5, performing gate etching, wherein the first and second polysilicon layers subjected to the gate etching respectively form a polysilicon floating gate and the polysilicon control gate; step 6, forming a first spacer, wherein the first spacer in a storage area fully fills a first interval area; and step 7, performing self-aligned ion implantation to increase a doping concentration of the polysilicon control gate to the target doping concentration.

Abstract: The present disclosure provides a method for manufacturing a semiconductor device, including: providing a substrate having a plurality of stacked gates with silicon nitride mask layer and silicon oxide mask layer formed on top of the surface; depositing a first carbon-containing silicon oxide thin layer; depositing a second non-carbon-containing silicon oxide layer to fill the gaps between adjacent stacked gates; and planarizing the first silicon oxide thin layer and the second silicon oxide layer by applying the silicon nitride mask layer as a stop layer, removing the second silicon oxide layer, and forming the first sidewalls with the first silicon oxide thin layer on the sides of the stacked gates. The present disclosure further provides a semiconductor device made with the method thereof. The present disclosure can remove the silicon oxide mask layer above the stacked gates through a simple process flow.

Abstract: The present disclosure provides a semiconductor device and a manufacturing method thereof. The manufacturing method comprises: providing a substrate comprising a storage region, forming stacked gates of storage transistors on the substrate; forming side walls on two sides of each stacked gate wherein the top surfaces of side walls are arranged to be lower than the top surfaces of the stacked gates; performing ion implantation in the storage region defined by the side walls; and performing an ashing process and a wet cleaning process using the side walls as protective layers of the stacked gates to remove a photoresist remaining after the ion implantation. The present disclosure further provides a semiconductor device formed according to the manufacturing method. According to the semiconductor device and the manufacturing method thereof, the problem of stacked gate collapse from the ion implantation process can be solved, thereby improving the yield.

Abstract: A method for forming the gate structure of the NAND memory, comprising the steps of disposing a gate structure layer, a pattern transfer layer, a TEOS structure, and an organic dielectric Tri-Layer on a substrate sequentially; performing a patterning using a first photomask and a first photoresist layer; performing an etching process to form a control gate structure, a peripheral gate structure and a select gate structure; performing a trimming process to them; patterning sidewalls on sides of them; performing a second patterning using a second photomask as a mask and a second photoresist layer to protect the peripheral gate structure, the select gate structure, and their sidewalls; removing the control gate structure between its sidewalls; performing etching by using the sidewalls, the peripheral gate structure and the select gate structure as masks to form the control gate, the peripheral gate, and the select gate.

Abstract: The present disclosure provides a method for manufacturing a semiconductor device, including: providing a substrate having a plurality of stacked gates with silicon nitride mask layer and silicon oxide mask layer formed on top of the surface; depositing a first carbon-containing silicon oxide thin layer; depositing a second non-carbon-containing silicon oxide layer to fill the gaps between adjacent stacked gates; and planarizing the first silicon oxide thin layer and the second silicon oxide layer by applying the silicon nitride mask layer as a stop layer, removing the second silicon oxide layer, and forming the first sidewalls with the first silicon oxide thin layer on the sides of the stacked gates . The present disclosure further provides a semiconductor device made with the method thereof. The present disclosure can remove the silicon oxide mask layer above the stacked gates through a simple process flow.

Abstract: The present disclosure provides a semiconductor device and a manufacturing method thereof. The manufacturing method comprises: providing a substrate comprising a storage region, forming stacked gates of storage transistors on the substrate; forming side walls on two sides of each stacked gate wherein the top surfaces of side walls are arranged to be lower than the top surfaces of the stacked gates; performing ion implantation in the storage region defined by the side walls; and performing an ashing process and a wet cleaning process using the side walls as protective layers of the stacked gates to remove a photoresist remaining after the ion implantation. The present disclosure further provides a semiconductor device formed according to the manufacturing method. According to the semiconductor device and the manufacturing method thereof, the problem of stacked gate collapse from the ion implantation process can be solved, thereby improving the yield.

Abstract: The present disclosure relates to the field of semiconductor device etching process, and specifically discloses an etching method and a semiconductor device. The etching method comprises: providing a substrate on which a film layer to be etched is formed; forming a mask layer structure on the film layer to be etched, wherein the mask layer structure includes a dielectric layer formed on an upper surface of the film layer to be etched and an APF layer formed on an upper surface of the dielectric layer; patterning the APF layer; performing a first etching process on the dielectric layer and the film layer to be etched by using the patterned APF layer as a mask to pattern the dielectric layer and partially etch the film layer to be etched; removing the patterned APF layer.

Abstract: The present invention provides a semiconductor structure and method of manufacturing the same. The semiconductor structure includes a substrate and a gate formed on the substrate. The above manufacturing method is used to form a gate on the substrate. The above manufacturing method specifically includes: providing a substrate; forming a trench in an upper portion of the substrate; depositing a gate layer on the substrate, the gate layer including two step portions extending from the outside of the trench to the inside of the trench; etching the gate layer from two ends of the trench along the two step portions toward the center of the trench to form the gate in the trench, wherein the width of the gate is smaller than the width of the trench. The manufacturing method of the present invention can easily and efficiently form a gate having a small critical dimension and precisely controllable on a semiconductor substrate, thereby meeting increasingly stringent gate size requirements.

Abstract: A method for forming the gate structure of the NAND memory, comprising the steps of disposing a gate structure layer, a pattern transfer layer, a TEOS structure, and an organic dielectric Tri-Layer on a substrate sequentially; performing a patterning using a first photomask and a first photoresist layer; performing an etching process to form a control gate structure, a peripheral gate structure and a select gate structure; performing a trimming process to them; patterning sidewalls on sides of them; performing a second patterning using a second photomask as a mask and a second photoresist layer to protect the peripheral gate structure, the select gate structure, and their sidewalls; removing the control gate structure between its sidewalls; performing etching by using the sidewalls, the peripheral gate structure and the select gate structure as masks to form the control gate, the peripheral gate, and the select gate.

Abstract: The present invention provides a semiconductor structure and method of manufacturing the same. The semiconductor structure includes a substrate and a gate formed on the substrate. The above manufacturing method is used to form a gate on the substrate. The above manufacturing method specifically includes: providing a substrate; forming a trench in an upper portion of the substrate; depositing a gate layer on the substrate, the gate layer including two step portions extending from the outside of the trench to the inside of the trench; etching the gate layer from two ends of the trench along the two step portions toward the center of the trench to form the gate in the trench, wherein the width of the gate is smaller than the width of the trench. The manufacturing method of the present invention can easily and efficiently form a gate having a small critical dimension and precisely controllable on a semiconductor substrate, thereby meeting increasingly stringent gate size requirements.

Abstract: The present disclosure relates to the field of semiconductor device etching process, and specifically discloses an etching method and a semiconductor device. The etching method comprises: providing a substrate on which a film layer to be etched is formed; forming a mask layer structure on the film layer to be etched, wherein the mask layer structure includes a dielectric layer formed on an upper surface of the film layer to be etched and an APF layer formed on an upper surface of the dielectric layer; patterning the APF layer; performing a first etching process on the dielectric layer and the film layer to be etched by using the patterned APF layer as a mask to pattern the dielectric layer and partially etch the film layer to be etched; removing the patterned APF layer.

Abstract: A manufacturing method of a Flash wafer, comprises: fabricating a Flash wafer containing a cell area, a logical area and a capacitance area; adjusting the height of the silicon oxide filled shallow trench in the logical area and the capacitance area; sequentially depositing a silicon nitride layer and a silicon oxide layer on the upper surface of the Flash wafer, and sequentially removing the silicon oxide layer and the silicon nitride layer on the upper surface of the cell area and on the upper surface of the floating gate in the logical area and the capacitance area; adjusting the height of the silicon oxide filled shallow trench in the cell area and the capacitance area; depositing an interlayer dielectric layer on the surface of the Flash wafer; removing the rest part in the logical area by protecting the cell area and the capacitance area with a mask.

Abstract: The present invention discloses a polysilicon fuse fabrication method. The polysilicon fuse comprises a polysilicon fuse-link and two leading terminals, the polysilicon fuse-link comprises a substrate, a first insulating layer and a polysilicon melt. The substrate is formed with a groove, which is covered by the first insulating layer. The polysilicon melt is formed on the first insulating layer and is embedded in the groove. Since the polysilicon melt is embedded in the groove of the substrate, the polysilicon melt is separated away from the nearby devices on the substrate by a sufficient safety distance, which effectively reduce or eliminate the effects of the particles generated during the blowing of the polysilicon melt on the nearby devices.

Abstract: The present invention discloses a polysilicon fuse and fabrication method thereof. The polysilicon fuse comprises a polysilicon fuse-link and two leading terminals, the polysilicon fuse-link comprises a substrate, a first insulating layer and a poly silicon melt. The substrate is formed with a groove, which is covered by the first insulating layer. The polysilicon melt is formed on the first insulating layer and is embedded in the groove. Since the polysilicon melt is embedded in the groove of the substrate, the polysilicon melt is separated away from the nearby devices on the substrate by a sufficient safety distance, which effectively reduce or eliminate the effects of the particles generated during the blowing of the polysilicon melt on the nearby devices.