Patents by Inventor Per Anders M. Franzén

Per Anders M. Franzén has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Formal verification coverage metrics for circuit design properties
    Patent number: 9177089
    Abstract: A computer-implemented method and non-transitory computer readable medium for circuit design verification. Formal verification is performed on a circuit design to prove a correctness of a property of the circuit design. The circuit design has a cone of influence representing a portion of the circuit design capable of affecting signals of the property. A proof core of the circuit design is identified, the proof core being a portion of the cone of influence that is sufficient to prove the correctness of the property. A coverage metric is generated that is indicative of a level of formal verification coverage provided by the property based on the proof core of the circuit design.
    Type: Grant
    Filed: September 1, 2014
    Date of Patent: November 3, 2015
    Assignee: Cadence Design Systems, Inc.
    Inventors: Ziyad E. Hanna, Per Anders M. Franzen, Ross M. Weber, Habeeb A. Farah, Rajeev K. Ranjan
  • FORMAL VERIFICATION COVERAGE METRICS FOR CIRCUIT DESIGN PROPERTIES
    Publication number: 20150135150
    Abstract: A computer-implemented method and non-transitory computer readable medium for circuit design verification. Formal verification is performed on a circuit design to prove a correctness of a property of the circuit design. The circuit design has a cone of influence representing a portion of the circuit design capable of affecting signals of the property. A proof core of the circuit design is identified, the proof core being a portion of the cone of influence that is sufficient to prove the correctness of the property. A coverage metric is generated that is indicative of a level of formal verification coverage provided by the property based on the proof core of the circuit design.
    Type: Application
    Filed: September 1, 2014
    Publication date: May 14, 2015
    Inventors: Ziyad E. Hanna, Per Anders M. Franzen, Ross M. Weber, Habeeb A. Farah, Rajeev K. Ranjan
  • Formal verification coverage metrics for circuit design properties
    Patent number: 8826201
    Abstract: A computer-implemented method and non-transitory computer readable medium for circuit design verification. Formal verification is performed on a circuit design to prove a correctness of a property of the circuit design. The circuit design has a cone of influence representing a portion of the circuit design capable of affecting signals of the property. A proof core of the circuit design is identified, the proof core being a portion of the cone of influence that is sufficient to prove the correctness of the property. A coverage metric is generated that is indicative of a level of formal verification coverage provided by the property based on the proof core of the circuit design.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: September 2, 2014
    Assignee: Jasper Design Automation, Inc.
    Inventors: Ziyad E. Hanna, Per Anders M. Franzén, Ross M. Weber, Habeeb A. Farah, Rajeev K. Ranjan