Abstract: A non-transitory computer readable medium includes stored instructions, which when executed by a processor, cause the processor to acquire a plurality of graphs that model results of a plurality of bug hunting searches for a register transfer level design, wherein the plurality of bug hunting searches determines a design error in the register transfer level design, construct a composite graph using the plurality of graphs, wherein the composite graph models a plurality of causal relationships between a plurality of detected bugs and a plurality of helper properties covered by the plurality of bug hunting searches, and execute an additional bug hunting search whose parameters are configured based on the composite graph.

Abstract: The fault analysis problem is modelled by automatically creating additional properties (fault properties) and constraints based on a plurality of injected faults and existing user assertions. These fault properties and constraints are sent to formal verification in a single run to qualify all of the faults together, rather than sequentially checking each fault in a separate formal verification run.

Abstract: Disclosed is a technology for parallelized design verification of two circuit designs at a register transfer level. A plurality of potential equivalent sub-circuit pairs is identified from the circuit designs to create a proof-tree structure. The proof-tree structure includes a root-proof, a plurality of parent-proofs downchain of said root-proof and a plurality of child-proofs downchain of at least one of the parent-proofs. Each one of the child-proofs is associated with a first equivalency status of one of the potential equivalent sub-circuit pairs. The parent-proofs are associated with second equivalency statuses dependent upon the first equivalency statuses of downchain child-proofs. The root-proof is associated with a third functional equivalency status of the two circuit designs dependent upon the second equivalency statuses of downchain parent-proofs. This Abstract is not intended to limit the scope of the claims.

Abstract: The fault analysis problem is modelled by automatically creating additional properties (fault properties) and constraints based on the injected faults and the existing user assertions. These fault properties and constraints are sent to formal verification in a single run to qualify all of the faults together, rather than sequentially checking each fault in a separate formal verification run.

Abstract: A method for functional verification includes transforming an original multiphase circuit design into a phase-abstracted circuit design by identifying cyclical (repetitive) signals in the multiphase circuit design, determining a number of simulation phases for the multiphase circuit design, unwinding the multiphase circuit design by the number of phases to create an unwound design, and then applying logic reduction techniques to the unwound design using the clock-like signals to reduce (simplify) the logic in the unwound design by eliminating unused/unnecessary registers, inputs, outputs, and logic. The resulting phase-abstracted design can then be processed much more efficiently by functional verification engines than the original multiphase circuit design due to the reduced number of registers/inputs.

Abstract: A method for functional verification includes transforming an original multiphase circuit design into a phase-abstracted circuit design by identifying cyclical (repetitive) signals in the multiphase circuit design, determining a number of simulation phases for the multiphase circuit design, unwinding the multiphase circuit design by the number of phases to create an unwound design, and then applying logic reduction techniques to the unwound design using the clock-like signals to reduce (simplify) the logic in the unwound design by eliminating unused/unnecessary registers, inputs, outputs, and logic. The resulting phase-abstracted design can then be processed much more efficiently by functional verification engines than the original multiphase circuit design due to the reduced number of registers/inputs.

Abstract: A method for functional verification includes transforming an original multiphase circuit design into a phase-abstracted circuit design by identifying cyclical (repetitive) signals in the multiphase circuit design, determining a number of simulation phases for the multiphase circuit design, unwinding the multiphase circuit design by the number of phases to create an unwound design, and then applying logic reduction techniques to the unwound design using the clock-like signals to reduce (simplify) the logic in the unwound design by eliminating unused/unnecessary registers, inputs, outputs, and logic. The resulting phase-abstracted design can then be processed much more efficiently by functional verification engines than the original multiphase circuit design due to the reduced number of registers/inputs.

Abstract: A method for functional verification includes transforming an original multiphase circuit design into a phase-abstracted circuit design by identifying cyclical (repetitive) signals in the multiphase circuit design, determining a number of simulation phases for the multiphase circuit design, unwinding the multiphase circuit design by the number of phases to create an unwound design, and then applying logic reduction techniques to the unwound design using the clock-like signals to reduce (simplify) the logic in the unwound design by eliminating unused/unnecessary registers, inputs, outputs, and logic. The resulting phase-abstracted design can then be processed much more efficiently by functional verification engines than the original multiphase circuit design due to the reduced number of registers/inputs.