Patents by Inventor Per Broms

Per Broms has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11190028
    Abstract: A battery management system having configurable batteries is disclosed. The battery management system generally includes (a) one or more cell control units, each cell control unit configured to control and/or balance a charge in a plurality of battery cells, and (b) a master controller in electrical communication with cell control unit(s). The cell control unit(s) as a whole include one or more switches, configured to be electrically connected to a first battery cell of a plurality of battery cells, and a resistor, a capacitor or an inductor electrically (i) connected to one switch and (ii) connected or connectable to a second battery cell. The master controller is configured to open or close each switch. The configurable battery generally includes a plurality of battery cells and switches configured to connect or disconnect the plurality of battery cells in a configurable or predetermined manner.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: November 30, 2021
    Assignee: Ensurge Micropower ASA
    Inventors: Christer Karlsson, Per Broms
  • Patent number: 7764529
    Abstract: In a non-volatile electric memory system a card-like memory unit (10) and a read/write unit (11) are provided as physically separate units. The memory unit (10) is based on a memory material (4) that can be set to at least two distinct physical states by applying an electric field across the memory material. The read/write unit (10) comprises contact means (9) provided in a determined geometrical pattern enabling a definition of memory cells in memory unit (10) in an initial write operation, the memory cells being located in a geometrical pattern corresponding to that of the contact means (9). Establishing a physical contact between the memory unit (10) and the read/write unit (11) closes an electrical circuit over an addressed memory cell such that read, write or erase operations can be effected.
    Type: Grant
    Filed: June 8, 2006
    Date of Patent: July 27, 2010
    Assignee: Thin Film Electronics ASA
    Inventors: Geirr I. Leistad, Per Broms, Christer Karlsson
  • Publication number: 20080198640
    Abstract: In a non-volatile electric memory system a card-like memory unit (10) and a read/write unit (11) are provided as physically separate units. The memory unit (10) is based on a memory material (4) that can be set to at least two distinct physical states by applying an electric field across the memory material. The read/write unit (10) comprises contact means (9) provided in a determined geometrical pattern enabling a definition of memory cells in memory unit (10) in an initial write operation, the memory cells being located in a geometrical pattern corresponding to that of the contact means (9). Establishing a physical contact between the memory unit (10) and the read/write unit (11) closes an electrical circuit over an addressed memory cell such that read, write or erase operations can be effected.
    Type: Application
    Filed: June 8, 2006
    Publication date: August 21, 2008
    Inventors: Geirr I. Leistad, Per Broms, Christer Karlsson
  • Publication number: 20080198644
    Abstract: In a non-volatile electric memory system a memory unit (4) and a read/write unit (11) are provided as physically separate units. The memory unit (10) is based on a memory material (4) that can be set to at least two distinct physical states by applying an electric field across the memory material. Electrode means and/or contact means are either provided in the memory unit or in the read/write unit and contact means are at least always provided in the read/write unit. Electrodes and contacts are provided in a geometrical arrangement, which defines geometrically one or more memory cells in the memory layer. Contact means in the read/write unit are provided connectable to driving, sensing and control means located in the read/write unit or in an external device connected with the latter. Establishing a physical contact between the memory unit and the read/write unit closes an electrical circuit over the addressed memory cell such that read, write or erase operations can be effected.
    Type: Application
    Filed: June 8, 2006
    Publication date: August 21, 2008
    Applicant: Thin Film Electronics ASA
    Inventors: Per Broms, Christer Karlsson, Geirr I. Leistad, Per Hamberg, Staffan Bjorklid, Johan Carlsson, Goran Gustafsson, Hans Gude Gudesen
  • Publication number: 20060007722
    Abstract: In a heating and temperature control system for a data storage apparatus comprising at least one matrix-addressable ferroelectric or electret memory device, Joule heating means are provided in the memory device, a temperature determining means is connected with controller circuitry and the controller circuitry is connected with an external power supply, which controlled by the former powers the Joule heating means to achieve a selected operating temperature. In a method for operating the heating and temperature control system an ambient or instant temperature of the memory device is determined and compared with the set nominal optimal temperature, and the difference between these temperatures is used in a predefined algorithm for establishing control parameters for the application of power to the Joule heating means to achieve the selected operating temperature in the memory device during an addressing operation thereto.
    Type: Application
    Filed: June 29, 2005
    Publication date: January 12, 2006
    Applicant: Thin Film Electronics ASA
    Inventors: Per-Erik Nordal, Geirr Leistad, Per Broms, Hans Gudesen
  • Publication number: 20050073869
    Abstract: A matrix-addressable ferroelectric or electret memory device and a method of operating are explained. The method includes applying a first plurality of voltage difference across a first and a second set of electrodes in the memory when data are read, and applying a second plurality of voltage differences when data are refreshed or rewritten. The first and second plurality of voltage differences correspond to sets of potential levels comprising time sequences of voltage pulses. At least one parameter indicative of a change in a memory cell response is used for determining at least one correction factor for the voltage pulses, whereby the pulse parameter is adjusted accordingly. The memory device comprises means for determining the at least one parameter, a calibration memory connected with means for determining the correction factor, and control circuits for adjusting pulse parameters as applied to read and write operations in the memory device.
    Type: Application
    Filed: September 11, 2003
    Publication date: April 7, 2005
    Inventors: Hans Gudesen, Per-Erik Nordal, Geirr Leistad, Per Broms, Per Sandstrom, Mats Johansson
  • Publication number: 20030103386
    Abstract: In a method for reading of a passive matrix-addressable device, particularly a memory device or a sensor device with individually addressable cells of a polarizable material, the cells store data in the form of one of two polarization states +Pr;−Pr in each cell, and the polarization states in the cells are written and read by addressing via electrodes which form word and bit lines (WL;BL) in an orthogonal electrode matrix, and wherein the cells are provided in or at the crossings between the word and bit lines (WL;BL) a voltage pulse protocol is used according to which electric potentials on all word and bit lines are controlled coordinated in time. During reading a word line (WL) is activated by applying voltage which relative to the potential on all crossing bit lines (BL) corresponds to the voltage Vs and data stored in the cells connected to this active word line (AWL) are determined by detecting the charge values of the cells in a detection means (SA).
    Type: Application
    Filed: November 7, 2002
    Publication date: June 5, 2003
    Inventors: Per Broms, Christer Karlsson
  • Publication number: 20020027794
    Abstract: In a method for performing read and write operations in a passive matrix-addressed memory array of memory cells comprising an electrically polarizable material exhibiting polarization remanence, in particular an electret or ferroelectric material, wherein a logical value stored in a memory cell is represented by an actual polarization state in the memory cell, a degree of polarization in the polarizable material is limited during each read and write cycle to a value defined by a circuit device controlling the read and write operations, with said value ranging from zero to an upper limit corresponding to saturation of the polarization and consistent with predetermined criterta for a reliable detection of a logic state of a memory cell.
    Type: Application
    Filed: July 6, 2001
    Publication date: March 7, 2002
    Inventors: Hans Gude Gudesen, Per-Erik Nordal, Per Broms, Mat Johansson