Abstract: A pluggable terminal block short circuit prevention system includes a pluggable terminal block having a computing device connector with positive and negative power sub-connectors that connect to a pluggable terminal block connector on a computing device. A power system connector is included on the pluggable terminal block and includes terminal block positive and negative power contacts that are coupled to the positive and negative power sub-connectors on the computing device connector, respectively. The power system connector couples to a power system via power cabling having a power cabling connector that includes power cabling connector positive and negative power contacts that are configured to engage the terminal block positive and negative power contacts when the power cabling connector is connected to the power system connector, with the power cabling connector preventing relative movement between the power cabling connector positive and negative power contacts.

Abstract: Embodiments herein provide more efficient, more flexible, and more cost-effective ways to provide additional and/or increased functionality to an information handling system. Presented herein are embodiments of an application acceleration port interface module (which embodiments may be referred to herein for convenience as “AAPIM”) into which pluggable I/O (input/output) modules may be inserted and the other ends inserted into ports of an information handling system to provide the information handling system with increase capabilities (e.g., increased resource, such as added processing, and increased services, such as new applications or accelerated services). AAPIM embodiments are versatile solutions to address application acceleration needs that can be quickly reprogrammed to address specific needs of a user.

Abstract: A timing signal diagnostic system includes a chassis housing an input system that receives a timing signal, a timing system that receives the timing signal from the input system, an analog-to-digital converter system that receives the timing signal from the input system, and a processing system that is coupled to the timing system and the analog-to-digital converter system. The processing system uses the timing system to output reference time signals to the analog-to-digital converter system that are based on the timing signal, and uses the analog-to-digital converter system to sample the timing signal based on the reference time signals over a plurality of different timing signal cycles. Based on the sampling of the timing signal, the processing system generates a waveform for the timing signal, and provides a timing signal diagnostic result based on the waveform for the timing signal.

Abstract: Hybrid deep learning systems and methods allow for detecting anomalies in objects, such as electrical printed circuit board (PCB) components, based on image data. In one or more embodiments, a hybrid deep learning model comprises a Graph Attention Network (GAT) that uses spatial properties of the PCB components to extract latent semantic information and generate an output set of hidden representations. The GAT treats each of the electrical components as a node and each connection between them as edges in a graph. The hybrid system further comprises a Convolutional Neural Network (CNN) that uses pixel data to obtain its own output set of hidden representations. The hybrid deep learning model concatenates both sets to detect anomalies that may be present on the PCB.

Abstract: Presented herein are systems and methods for packet processing in an information handling system that uses loopback processing. In one or more embodiments, buffer accounting is done with respect to the original ingress port for packets when using loopback processing. Such embodiments have several benefits, including but not limited to, mitigating or eliminating head-of-line (HoL) blocking of traffic and headroom (plus additional buffers which may need to be allocated for use before priority-based flow control is generated) provisioning for the loopback port. Embodiments may include additional features, such as handling anomalies (e.g., corruption) and reclaiming reserved buffers if corruption or delays occur.

Abstract: Embodiments herein provide more efficient, more flexible, and more cost-effective ways to provide additional and/or increased functionality to an information handling system. Presented herein are embodiments of an application acceleration port interface module (which embodiments may be referred to herein for convenience as “AAPIM”) into which pluggable I/O (input/output) modules may be inserted and the other ends inserted into ports of an information handling system to provide the information handling system with increase capabilities (e.g., increased resource, such as added processing, and increased services, such as new applications or accelerated services). AAPIM embodiments are versatile solutions to address application acceleration needs that can be quickly reprogrammed to address specific needs of a user.

Abstract: An apparatus comprises two or more connection ports, at least one wireless network interface, and at least one processing device comprising a processor coupled to a memory. The at least one processing device is configured to receive, utilizing a first one of the two or more connection ports, a first type of out-of-band management traffic from a managed information technology asset, to receive, utilizing a second one of the two or more connection ports, a second type of out-of-band management traffic from the managed information technology asset, and to communicate, via the at least one wireless network interface, the first and second types of out-of-band management traffic to one or more additional processing devices.

Abstract: A power supply system includes an AC input device/DC input device connector having an AC input device sub-connector and a DC input device sub-connector, an AC power supply subsystem configured to perform first power operation(s) on first power received from the AC input device sub-connector, and a DC power supply subsystem configured to perform second power operation(s) on second power received from the DC input device sub-connector. When an AC input device is coupled to the AC input device sub-connector, an AC-or-DC power supply subsystem in the power supply system performs third power operation(s) on the first power received from the AC power supply subsystem, and supplies it to component(s). When the DC input device is coupled to the DC input device sub-connector, the AC-or-DC power supply subsystem performs the third power operation(s) on the second power received from the DC power supply subsystem, and supplies it to component(s).

Abstract: A method for manufacturing networking devices includes providing circuit boards each having an NPU mounted to that circuit board, and respective cable connectors mounted to that circuit board and coupled to that NPU. First networking devices are manufactured by providing one of the circuit boards in a chassis in each first networking device, and cabling at least some of the cable connectors on that circuit board to first subsystem(s) in that first networking device in order to configure that first networking device to perform first functionality. Second networking devices are manufactured by providing a respective one of the circuit boards in a chassis in each second networking device, and cabling at least some of the cable connectors on that circuit board to second subsystem(s) in that second networking device in order to configure that second networking device to perform second functionality that is different than the first functionality.

Abstract: A twisted-pair cable serial console communication adapter system includes a networking device including a first serial console connector, a twisted-pair cable including a first twisted-pair cable connector, and a first twisted-pair cable serial console communication adapter device that is connected to the first serial console connector and the first twisted-pair cable connector. The first twisted-pair cable serial console communication adapter device receives first signals via a first transmit pin on the first serial console connector, and provides the first signals to a first twisted-pair conductor in the twisted-pair cable. The first twisted-pair cable serial console communication adapter device also receives second signals via a second twisted-pair conductor in the twisted-pair cable, and provides the second signals to a first receive pin on the first serial console connector.

Abstract: A twisted-pair cable serial console communication adapter system includes a networking device including a first serial console connector, a twisted-pair cable including a first twisted-pair cable connector, and a first twisted-pair cable serial console communication adapter device that is connected to the first serial console connector and the first twisted-pair cable connector. The first twisted-pair cable serial console communication adapter device receives first signals via a first transmit pin on the first serial console connector, and provides the first signals to a first twisted-pair conductor in the twisted-pair cable. The first twisted-pair cable serial console communication adapter device also receives second signals via a second twisted-pair conductor in the twisted-pair cable, and provides the second signals to a first receive pin on the first serial console connector.

Abstract: A high-density networking system includes first networking device(s) coupled to a second networking device. The second networking device has a port row including first ports and a first subset of third ports, and second ports and a second subset of third ports that are each moveable relative to the first ports and the first subset of third ports, with the third ports coupled to the first networking device(s). The second networking device includes a switch device coupling the third ports to its processing system. The switch device in second networking device routes data from the processing system through a network via the first subset of third ports/first networking device(s), determines that data received from the processing system cannot reach the network via the first subset of third ports and, in response, routes data received from the processing system through the network via the second subset of third ports/first networking device(s).

Abstract: An apparatus comprises a processing device configured to generate connectivity information associated with at least one of a first device coupled to a first cable connector at a first end of a cable and a second device coupled to a second cable connector at a second end of the cable opposite the first end of the cable. The processing device is also configured to provision, via an integrated sideband interface of the cable, the generated connectivity information for display on at least one of a first cable display proximate the first cable connector at the first end of the cable and a second cable display proximate the second cable connector at the second end of the cable.

Abstract: An apparatus comprises a processing device configured to generate connectivity information associated with at least one of a first device coupled to a first cable connector at a first end of a cable and a second device coupled to a second cable connector at a second end of the cable opposite the first end of the cable. The processing device is also configured to provision, via an integrated sideband interface of the cable, the generated connectivity information for display on at least one of a first cable display proximate the first cable connector at the first end of the cable and a second cable display proximate the second cable connector at the second end of the cable.

Abstract: A Reconfigurable Intelligent Surface (RIS)/Light Fidelity (LiFi) rack communication system includes a rack that includes a computing device, a LiFi device that transmits first light-modulated data, and a RIS system. The RIS system includes a RIS device that directs the first light-modulated data transmitted by the LiFi Device at the computing device, and a RIS control subsystem that is coupled to the at least one RIS device. The RIS control subsystem determines a first signal integrity of the first light-modulated data received by the computing device via the RIS device when the RIS device includes a first configuration, and reconfigures the RIS device with a second configuration such that the first light-modulated data received by the computing device via the RIS device includes a second signal integrity that is greater than the first signal integrity.

Abstract: A high-density networking system includes first networking device(s) coupled to a second networking device. The second networking device has a port row including first ports and a first subset of third ports, and second ports and a second subset of third ports that are each moveable relative to the first ports and the first subset of third ports, with the third ports coupled to the first networking device(s). The second networking device includes a switch device coupling the third ports to its processing system. The switch device in second networking device routes data from the processing system through a network via the first subset of third ports/first networking device(s), determines that data received from the processing system cannot reach the network via the first subset of third ports and, in response, routes data received from the processing system through the network via the second subset of third ports/first networking device(s).

Abstract: Hybrid deep learning systems and methods allow for detecting anomalies in objects, such as electrical printed circuit board (PCB) components, based on image data. In one or more embodiments, a hybrid deep learning model comprises a Graph Attention Network (GAT) that uses spatial properties of the PCB components to extract latent semantic information and generate an output set of hidden representations. The GAT treats each of the electrical components as a node and each connection between them as edges in a graph. The hybrid system further comprises a Convolutional Neural Network (CNN) that uses pixel data to obtain its own output set of hidden representations. The hybrid deep learning model concatenates both sets to detect anomalies that may be present on the PCB.

Abstract: A modular networking device connection system includes a modular networking system chassis that defines a modular networking device slot. An internal wall is located in immediately adjacent the modular networking device slot, and includes a internal wall connector that connects to a modular networking device positioned in the modular networking device slot. A networking processing device is located opposite the internal wall, and includes a networking processor that is mounted to a networking processing device board and coupled via at least one trace to a networking processing device connector that is mounted to the networking processing device board. The networking processing device connector is directly connected to the internal wall connector by a first cable that transmits signals received through the internal wall connector directly to the networking processing device connector for provision to the networking processor via the networking processing device board.

Abstract: A modular networking device connection system includes a modular networking system chassis that defines a modular networking device slot. An internal wall is located in immediately adjacent the modular networking device slot, and includes a internal wall connector that connects to a modular networking device positioned in the modular networking device slot. A networking processing device is located opposite the internal wall, and includes a networking processor that is mounted to a networking processing device board and coupled via at least one trace to a networking processing device connector that is mounted to the networking processing device board. The networking processing device connector is directly connected to the internal wall connector by a first cable that transmits signals received through the internal wall connector directly to the networking processing device connector for provision to the networking processor via the networking processing device board.

Abstract: The present invention relates to an apparatus and a method for sigma-delta modulation with a reduced periodic noise (idle noise) in a sigma-delta modulator. The reduction is achieved by means of addition of two different Dither signals (217,218) to the sigma-delta modulator. A first Dither signal (218) is constituted by a particular bit pattern of a certain period while a second Dither signal (217) is constituted by a pseudo-random signal of a certain other period.