Abstract: Selectively enabling an amplitude processing circuit and a phase processing circuit of a wireless station's polar receiver with respect to reception of a beacon signal. Such systems and methods may include sequentially demodulating symbols of the received beacon signal using at least the phase processing circuit to detect a traffic indication signal value in a data payload portion of the received beacon signal. Upon detecting a condition indicating no data traffic for the wireless station, the phase processing circuit may be turned off. The polar receiver may demodulate symbols of the received beacon signal and upon detecting a beacon preamble symbol sequence, shut off the amplitude processing circuit and set the amplitude to a fixed value. The phase processing circuit in conjunction with the fixed amplitude value may be used to demodulate symbols of the beacon signal.

Abstract: An example method in accordance with some embodiments includes: determining an output frequency control word (FCW) having a plurality of bits, the output FCW being configured to control an oscillator, the oscillator including a plurality of capacitor banks, the plurality of capacitor banks respectively corresponding to the plurality of bits of the output FCW; storing the output FCW in a clocked delay cell; providing an input clock to the clocked delay cell, wherein the input clock is provided to delay the output FCW by an amount of delay; and, in accordance with the input clock, releasing the delayed output FCW from the clocked delay cell, and respectively applying the plurality of bits of the delayed output FCW to the plurality of capacitor banks of the oscillator.

Abstract: Selectively enabling an amplitude processing circuit and a phase processing circuit of a wireless station's polar receiver with respect to reception of a beacon signal. Such systems and methods may include sequentially demodulating symbols of the received beacon signal using at least the phase processing circuit to detect a traffic indication signal value in a data payload portion of the received beacon signal. Upon detecting a condition indicating no data traffic for the wireless station, the phase processing circuit may be turned off. The polar receiver may demodulate symbols of the received beacon signal and upon detecting a beacon preamble symbol sequence, shut off the amplitude processing circuit and set the amplitude to a fixed value. The phase processing circuit in conjunction with the fixed amplitude value may be used to demodulate symbols of the beacon signal.

Abstract: A method and circuit for linearizing a frequency response of an oscillator controlled by a plurality of capacitor banks are disclosed. In the disclosed method, for each capacitor bank of at least two capacitor banks of the oscillator, a respective sensitivity characteristic of the capacitor bank is determined. Further, a set of reference output frequency control words (FCWs) for an associated set of frequencies of the oscillator are determined. When an input FCW is received and an output FCW is responsively provided based on (i) an interpolation between two reference output FCWs of the set of reference output FCWs and (ii) the respective sensitivity characteristics of the at least two capacitor banks of the oscillator. The output FCW is then applied to the at least two capacitor banks of the oscillator.

Abstract: An example method in accordance with some embodiments includes: determining an output frequency control word (FCW) having a plurality of bits, the output FCW being configured to control an oscillator, the oscillator including a plurality of capacitor banks, the plurality of capacitor banks respectively corresponding to the plurality of bits of the output FCW; storing the output FCW in a clocked delay cell; providing an input clock to the clocked delay cell, wherein the input clock is provided to delay the output FCW by an amount of delay; and, in accordance with the input clock, releasing the delayed output FCW from the clocked delay cell, and respectively applying the plurality of bits of the delayed output FCW to the plurality of capacitor banks of the oscillator.

Abstract: Systems and methods for up-sampling a polar amplitude sample stream in a polar modulator are disclosed. In some embodiments, a process includes receiving, at a polar modulator, an in-phase sample stream and a quadrature sample stream which together characterize a data signal in an IQ plane. The process includes generating a polar amplitude sample stream and a polar phase sample stream. The process includes generating an up-sampled polar amplitude sample stream by (i) identifying an origin crossing of the data signal in the IQ plane, (ii) responsively adjusting an inversion trigger, (iii) selectively applying an inversion to the polar amplitude sample stream based on the inversion trigger, (iv) interpolating the selectively inverted polar amplitude sample stream, and (v) removing the inversion from the interpolated selectively inverted polar amplitude sample stream. The process includes modulating a carrier signal using the up-sampled polar amplitude stream and the polar phase sample stream.

Abstract: Selectively enabling an amplitude processing circuit and a phase processing circuit of a wireless station's polar receiver with respect to reception of a beacon signal. Such systems and methods may include sequentially demodulating symbols of the received beacon signal using at least the phase processing circuit to detect a traffic indication signal value in a data payload portion of the received beacon signal. Upon detecting a condition indicating no data traffic for the wireless station, the phase processing circuit may be turned off. The polar receiver may demodulate symbols of the received beacon signal and upon detecting a beacon preamble symbol sequence, shut off the amplitude processing circuit and set the amplitude to a fixed value. The phase processing circuit in conjunction with the fixed amplitude value may be used to demodulate symbols of the beacon signal.

Abstract: Selectively enabling an amplitude processing circuit and a phase processing circuit of a wireless station's polar receiver with respect to reception of a beacon signal. Such systems and methods may include sequentially demodulating symbols of the received beacon signal using at least the phase processing circuit to detect a traffic indication signal value in a data payload portion of the received beacon signal. Upon detecting a condition indicating no data traffic for the wireless station, the phase processing circuit may be turned off. The polar receiver may demodulate symbols of the received beacon signal and upon detecting a beacon preamble symbol sequence, shut off the amplitude processing circuit and set the amplitude to a fixed value. The phase processing circuit in conjunction with the fixed amplitude value may be used to demodulate symbols of the beacon signal.

Abstract: Systems and methods for up-sampling a polar amplitude sample stream in a polar modulator are disclosed. In some embodiments, a process includes receiving, at a polar modulator, an in-phase sample stream and a quadrature sample stream which together characterize a data signal in an IQ plane. The process includes generating a polar amplitude sample stream and a polar phase sample stream. The process includes generating an up-sampled polar amplitude sample stream by (i) identifying an origin crossing of the data signal in the IQ plane, (ii) responsively adjusting an inversion trigger, (iii) selectively applying an inversion to the polar amplitude sample stream based on the inversion trigger, (iv) interpolating the selectively inverted polar amplitude sample stream, and (v) removing the inversion from the interpolated selectively inverted polar amplitude sample stream. The process includes modulating a carrier signal using the up-sampled polar amplitude stream and the polar phase sample stream.

Abstract: A method and circuit for linearizing a frequency response of an oscillator controlled by a plurality of capacitor banks are disclosed. In the disclosed method, for each capacitor bank of at least two capacitor banks of the oscillator, a respective sensitivity characteristic of the capacitor bank is determined. Further, a set of reference output frequency control words (FCWs) for an associated set of frequencies of the oscillator are determined. When an input FCW is received and an output FCW is responsively provided based on (i) an interpolation between two reference output FCWs of the set of reference output FCWs and (ii) the respective sensitivity characteristics of the at least two capacitor banks of the oscillator. The output FCW is then applied to the at least two capacitor banks of the oscillator.

Abstract: Systems and methods for up-sampling a polar amplitude sample stream in a polar modulator are disclosed. In some embodiments, a process includes receiving, at a polar modulator, an in-phase sample stream and a quadrature sample stream which together characterize a data signal in an IQ plane. The process includes generating a polar amplitude sample stream and a polar phase sample stream. The process includes generating an up-sampled polar amplitude sample stream by (i) identifying an origin crossing of the data signal in the IQ plane, (ii) responsively adjusting an inversion trigger, (iii) selectively applying an inversion to the polar amplitude sample stream based on the inversion trigger, (iv) interpolating the selectively inverted polar amplitude sample stream, and (v) removing the inversion from the interpolated selectively inverted polar amplitude sample stream. The process includes modulating a carrier signal using the up-sampled polar amplitude stream and the polar phase sample stream.

Abstract: This invention can generally be described as an overall transmit (TX) scheduler state-machine that is broken down into two different state-machines: One first TX-scheduler state-machine (FTSM), executed in software, and one second TX-scheduler state-machine (STSM) executed in hardware, which is operating in four different basic states. The functional partitioning between the two state-machines is such that the most constrained real-time requirements are allocated to the STSM, while all complex decisions and non time-critical controls are allocated to the FTSM. The invention also relates to a terminal comprising the invented transmit scheduler.

Abstract: This invention can generally be described as an overall transmit (TX) scheduler state-machine that is broken down into two different state-machines: One first TX-scheduler state-machine (FTSM), executed in software, and one second TX-scheduler state-machine (STSM) executed in hardware, which is operating in four different basic states. The functional partitioning between the two state-machines is such that the most constrained real-time requirements are allocated to the STSM, while all complex decisions and non time-critical controls are allocated to the FTSM. The invention also relates to a terminal comprising the invented transmit scheduler.

Abstract: A method for controlling gain of an amplifier includes amplifying one or more received signals to produce one or more amplified signals. The method also includes generating a plurality of down converted signals using the one or more amplified signals. The method further includes amplifying the plurality of down converted signals based on a gain control signal. In addition, the method includes varying a time constant of the gain control signal based on a time derivative parameter associated with the plurality of down converted signals.

Abstract: A Wireless Local Area Network (WLAN) station/terminal operates in normally mutually exclusive infrastructure and independent modes. A mixed mode is added by means of a mixed mode means for running the WLAN terminal in the infrastructure and independent modes simultaneously.

Abstract: An adjustable phase shifter generates a phase shifted reference signal by introducing a phase shift in a reference signal. A phase detector identifies a phase difference between the reference signal and the phase shifted reference signal. A control signal generator generates a plurality of control signals, each of which causes the adjustable phase shifter to adjust a magnitude of at least one component value in the adjustable phase shifter. The phase shift introduced by the adjustable phase shifter is based at least partially on the magnitude of the at least one component value in the adjustable phase shifter. The control signal generator also selects one of the control signals, where the selected control signal causes the adjustable phase shifter to produce the phase shifted reference signal such that the phase difference attains a specified value. The analog filter adjusts a magnitude of at least one component value in the analog filter based at least partially on the selected control signal.

Abstract: The invention relates to trimming of analogue filters (201) in integrated circuits by means of an automatic adjusting circuit. A local oscillator (202) in the automatic adjusting circuit provides a periodic reference signal (R) to an adjustable phase shifter (203), which on basis thereof, produces a periodic phase shifted signal (R*). A phase detector (204) receives both the periodic reference signal (R) and the phase shifted period signal (R*) and produces a test signal (T) in response to a phase difference between the periodic reference signal (R) and the periodic phase shifted signal (R8). A lowpass filter (205) receives the test signal (T) and generates a level signal (TDC) relative a reference level, e.g. representing a zero voltage. A digital signal processor (207) produces a primary control signal (CS), having a serial format, on basis of the observation signal (M). A serial-to-parallel converter (208) converts the primary control signal (CS) into a control signal (CP) having a parallel signal format.

Abstract: The invention relates to trimming of analogue filters (201) in integrated circuits by means of an automatic adjusting circuit. A local oscillator (202) in the automatic adjusting circuit provides a periodic reference signal (R) to an adjustable phase shifter (203), which on basis thereof, produces a periodic phase shifted signal (R*). A phase detector (204) receives both the periodic reference signal (R) and the phase shifted period signal (R*) and produces a test signal (T) in response to a phase difference between the periodic reference signal (R) and the periodic phase shifted signal (R8). A lowpass filter (205) receives the test signal (T) and generates a level signal (TDC) relative a reference level, e.g. representing a zero voltage. A digital signal processor (207) produces a primary control signal (CS), having a serial format, on basis of the observation signal (M). A serial-to-parallel converter (208) converts the primary control signal (CS) into a control signal (CP) having a parallel signal format.

Abstract: The invention relates to gain control for an amplifier for received radio signals by means of an automatic gain control signal (c). A down converter (103) produces signal components (I; Q) from received radio frequency signals (RF). The signal components (I; Q) are amplified in a respective amplifier (104; 105), low pass filtered (106; 107) and further amplified (108; 109). Then, the resulting signal components (IP-LP; Q−LP) are digitised in A/D-converters (110; 111 ) for further processing in a digital signal processor (112). The resulting signal components (IP-LP; QP-LP) are also fed to a respective signal level detector (113; 114) whose output signals ([I]; [Q]) are combined (115) into a combined signal (V&Sgr;). This signal (V&Sgr;) is forwarded to a gain control unti (116), which produces the automatic gain control signal (c).

Abstract: Synchronization is effected in a cellular telecommunications network between a timing unit located at control node (e.g., RNC) of the network and a slave timing unit (STU) located at a controlled node (e.g., base station) of the network. Upon determining that a synchronization adjustment of the slave timing unit is necessary, an adjustment signal (e.g., voltage signal) is caused to be input to the oscillator of the slave timing unit in order to change the frequency of the slave's oscillator. Frame counter(s), in communication with the oscillator at the slave timing unit, will thus follow the oscillator continuously with smooth phase adjustments. By avoiding a direct adjustment of the frame counter(s), undesirable phase jumps or steps are avoided that can potentially disturb the air-interface between a base station and mobile station (MS).