Abstract: A method and mechanism are managing caches. A cache is configured to store blocks of data based upon predictions of future accesses. Each block is partitioned into sub-blocks, and if it is predicted a given sub-block is unlikely to be accessed, the sub-block may not be stored in the cache. Associated with each block is a mask which indicates whether sub-blocks of the block are likely to be accessed. When a block is first loaded into the cache, the corresponding mask is cleared and an indication is set for the block to indicate a training mode for the block. Access patterns of the block are then monitored and stored in the mask. If a given sub-block is accessed a predetermined number of times, a bit in the mask is set to indicate that the sub-block is likely to be accessed. When a block is evicted from the cache, the mask is also transferred for storage and only the sub-blocks identified by the mask as being likely to be accessed may be transferred for storage.

Abstract: A computing system comprises a processor, a data storage unit, and a block size table (BST). The processor includes at least one cache configured to store data. The data storage unit is configured to store data in a compressed format in fixed size units. The BST is configured to store block size entries corresponding to data blocks stored in the data storage unit. In response to a miss in the cache corresponding to a target data block, the processor is configured to identify an entry in the BST corresponding to the target data block, utilize information stored in the entry to determine the location of the target data block in the data storage unit, and cause the target data block to be retrieved from the data storage unit, decompressed, and stored in the cache.

Abstract: A method for managing a computer system process memory allocated to execution of a process configured to use data stored to storage is provided. The process memory has a predetermined size and is filled by uncompressed pages of data necessary to execute the process being copied from the storage. The process memory is partitioned into an uncompressed region having an adjustable first size and a compressed region having an adjustable second size. The uncompressed region includes uncompressed pages of data and the compressed region includes compressed pages of data. The first size of the uncompressed region and the second size of the compressed region are adjusted when a requested page of data necessary for continuing the execution of the process resides in either the storage or the compressed region.

Abstract: A coherence prediction mechanism includes a synchronization manager and a plurality of access predictors. The synchronization manager maintains one or more sequence entries, each sequence entry indicating a sequence in which a corresponding data block is accessed by two or more processing elements of a multiprocessor system. An access predictor provides a prediction to the synchronization manager identifying a next data block to be accessed by a corresponding processing element. In response to an indication of an access to a particular data block from a first processing element, the synchronization manager accesses a sequence entry corresponding to the particular data block and sends an identification of a next processing element expected to access the data block to the first processing element. The first processing element may use the identification to perform one or more speculative coherence actions.

Abstract: In one embodiment, a cache comprises a cache memory and a cache control circuit coupled to the cache memory. The cache memory is configured to store a plurality of cache blocks and a plurality of cache states. Each of the plurality of cache states corresponds to a respective one of the plurality of cache blocks. The cache control circuit is configured to implement a cache coherency protocol that includes a plurality of stable states and a transient state The transient state may be used in response to any request from a local consumer if completing the request includes a change between the plurality of stable states and making the change includes transmitting at least a first communication to maintain coherency on an interconnect.

Abstract: A coherence prediction mechanism includes a history cache for storing a plurality of cache entries each storing coherence history information for a corresponding block of data. Entries in the history cache are used to index into a pattern memory containing coherence predictions.

Abstract: A coherence prediction mechanism includes a history cache for storing a plurality of cache entries each storing coherence history information for a corresponding block of data. Entries in the history cache are used to index into a pattern memory containing coherence predictions.