Abstract: Methods for promoting interface bonding energy utilized in SOI technology are provided. In one embodiment, the method for promoting interface bonding energy includes providing a first substrate and a second substrate, wherein the first substrate has a silicon oxide layer formed thereon and a cleavage plane defined therein, performing a dry cleaning process on a surface of the silicon oxide layer and a surface of the second substrate, and bonding the cleaned silicon oxide surface of the first substrate to the cleaned surface of the second substrate.

Abstract: Methods for cleaning substrate surfaces utilized in SOI technology are provided. In one embodiment, the method for cleaning substrate surfaces includes providing a first substrate and a second substrate, wherein the first substrate has a silicon oxide layer formed thereon and a cleavage plane defined therein, performing a wet cleaning process on the surfaces of the first substrate and the second substrate, and bonding the cleaned silicon oxide layer to the cleaned surface of the second substrate.

Abstract: Methods for promoting interface bonding energy utilized in SOI technology are provided. In one embodiment, the method for promoting interface bonding energy includes providing a first substrate and a second substrate, wherein the first substrate has a silicon oxide layer formed thereon and a cleavage plane defined therein, performing a dry cleaning process on a surface of the silicon oxide layer and a surface of the second substrate, and bonding the cleaned silicon oxide surface of the first substrate to the cleaned surface of the second substrate.

Abstract: Aspects of the invention generally provide an apparatus and method for processing substrates using a multi-chamber processing system that is adapted to process substrates and analyze the results of the processes performed on the substrate. In one aspect of the invention, one or more analysis steps and/or pre-processing steps are performed on the substrate to provide data for processes performed on subsequent substrates. In one aspect of the invention, a system controller and one or more analysis devices are utilized to monitor and control a process chamber recipe and/or a process sequence to reduce substrate scrap due to defects in the formed device and device performance variability issues. Embodiments of the present invention also generally provide methods and a system for repeatably and reliably forming semiconductor devices used in a variety of applications.

Abstract: Aspects of the invention generally provide an apparatus and method for processing substrates using a multi-chamber processing system that is adapted to process substrates and analyze the results of the processes performed on the substrate. In one aspect of the invention, one or more analysis steps and/or precleaning steps are utilized to reduce the effect of queue time on device yield. In one aspect of the invention, a system controller and the one or more analysis chambers are utilized to monitor and control a process chamber recipe and/or a process sequence to reduce substrate scrap due to defects in the formed device and device performance variability issues. Embodiments of the present invention also generally provide methods and a system for repeatably and reliably forming semiconductor devices used in a variety of applications.

Abstract: A process kit for a semiconductor process chamber is provided herein. In one embodiment, a process kit for a semiconductor processing chamber, includes one or more components fabricated from a metal-free sintered silicon carbide material. The process kit comprises at least one of a substrate support, a pre-heat ring, lift pins, and substrate support pins. In another embodiment, a semiconductor process chamber is provided, having a chamber body and a substrate support disposed in the chamber body. The substrate support is fabricated from metal-free sintered silicon carbide. Optionally, the process chamber may include a process kit having at least one component fabricated from a metal-free sintered silicon carbide.

Abstract: A CVD reactor has an upper reactor chamber (2), a lower reactor chamber (3) and a dividing wall (4) that has a circular hole (5) in which a holding ring (6) for a wafer (7) is positioned. A process for producing an epitaxially coated semiconductor wafer includes the following: a) placing a semiconductor wafer in a CVD reactor having an upper reactor chamber (2), a lower reactor chamber (3) and a dividing wall (4) that has a circular hole (5) in which a holding ring (6) for a wafer is positioned, b) heating the semiconductor wafer using heat sources, c) depositing a protective layer on the back of the semiconductor wafer, d) depositing an epitaxial layer on the front of the semiconductor wafer, and e) removing the epitaxially coated semiconductor wafer from the CVD reactor.

Abstract: A method and device for detecting an incorrect position of a semiconductor wafer during a high-temperature treatment of the semiconductor water in a quartz chamber which is heated by IR radiators, has the semiconductor wafer lying on a rotating support and being held at a specific temperature with the aid of a control system. Thermal radiation which is emitted by the semiconductor wafer and the IR radiators is recorded using a pyrometer. The radiation temperature of the recorded thermal radiation is determined. The semiconductor wafer is assumed to be in an incorrect position if the temperature of the recorded thermal radiation fluctuates to such an extent over the course of time that the fluctuation width lies outside a fluctuation range &Dgr;T which is regarded as permissible.

Abstract: To produce a layer by liquid-phase heteroepitaxy a molten metal serving as the solvent is saturated at a first temperature with substrate material and compounded with layer material. The solution and the substrate are then separatly "overheated" to a second, higher temperature and then brought into contact with each other. Due to the overheating a negative thermodynamic driving force results for the epitaxy which compensates the positive driving force for the epitaxy at least in part due to the different interfacial energies between layer material and solution and substrate material and solution. The degree of overheating determines the resulting total driving force for the epitaxy which may be reduced to zero. Very thin layers, down to a monolayer thickness may be grown in this way from the solution with a layer thickness exact to a monolayer with no dislocation.