Abstract: Systems, methods, and apparatuses including computer program products for speculative throughput computing are disclosed. Speculative throughput computing is used to execute program segments in parallel.

Abstract: Dynamic pointer analysis techniques are able to produce faster pointer dependency test code and analyze more complex code in high-level languages such as in the programming languages C and C++ (not excluding other languages), as compared to known techniques.

Abstract: Systems, methods, and apparatuses including computer program products for speculative throughput computing are disclosed. Speculative throughput computing is used to translate a program to execute on a plurality of processors, processor cores, or threads.

Abstract: Systems, methods, and apparatuses including computer program products for speculative throughput computing are disclosed. Speculative throughput computing is used to execute program segments in parallel.

Abstract: Systems, methods, and apparatuses including computer program products for speculative throughput computing are disclosed. Speculative throughput computing is used to reduce a number of miss-speculations during execution of program segments in parallel.

Abstract: In one embodiment, a cache comprises a cache memory and a cache control circuit coupled to the cache memory. The cache memory is configured to store a plurality of cache blocks and a plurality of cache states. Each of the plurality of cache states corresponds to a respective one of the plurality of cache blocks. The cache control circuit is configured to implement a cache coherency protocol that includes a plurality of stable states and a transient state The transient state may be used in response to any request from a local consumer if completing the request includes a change between the plurality of stable states and making the change includes transmitting at least a first communication to maintain coherency on an interconnect.

Abstract: A multiprocessor system is described including a plurality of processors. At least one level of cache memory is operatively connected to each of the processors. At least one memory unit is shared by at least two of the processors. A status memory, in correspondence to each processor, is configured to store a current status in correspondence to memory regions capable of being stored in the cache memories. The current status indicates whether a memory region is non-shared. The system includes logic, in correspondence to and operatively connected to each processor, for generating minimum cache-coherence activities in response to a memory access request by a respective processor.