Patents by Inventor Perceval Coudrain
Perceval Coudrain has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240128227Abstract: A SiP-type electronic device, including an electronic chip provided with an electrical interconnection face; a redistribution layer electrically coupled to the electrical interconnection face of the chip; electrical connection elements electrically coupled to the chip by the redistribution layer which is arranged between the chip and the connection elements; a first metal layer arranged on the side of a second face of the chip and secured to this second face; an encapsulation material arranged around the chip, between the redistribution layer and the first metal layer; a second metal layer including a first face secured by direct bonding to the first metal layer; a substrate arranged against a second face of the second metal layer.Type: ApplicationFiled: October 13, 2023Publication date: April 18, 2024Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Perceval COUDRAIN, Arnaud GARNIER, Jeanne PIGNOL
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Publication number: 20240097721Abstract: An integration system and method for the manufacture of radio frequency transmission front-end modules with radio frequency integrated circuit(s) and self-biased magnetic component(s) integrated on a “Wafer Level Packaging”-type technology. This integration makes it possible to design efficient, compact and low-cost front-end modules.Type: ApplicationFiled: September 20, 2023Publication date: March 21, 2024Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Ayssar SERHAN, Pascal REYNIER, Alexandre GIRY, Perceval COUDRAIN, Jean-Philippe MICHEL
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Patent number: 11823997Abstract: A functional chip includes a substrate including a first face and a second face, the second face of the substrate forming the front face of the functional chip; a first oxide layer on the first face of the substrate; a second oxide layer on the first oxide layer; a first routing level formed on the surface of the second oxide layer in contact with the first oxide layer; a third oxide layer on the second oxide layer wherein a semiconductor component is inserted; a rear face formed by the surface of the third oxide layer opposite the second oxide layer, the rear face including superconductor routing tracks surrounded at least partially by one or more conductor routing tracks, the semiconductor component being connected to the superconductor routing tracks via superconductor vias and the conductor routing tracks of the rear face being connected to the routing level via conductor vias.Type: GrantFiled: September 20, 2021Date of Patent: November 21, 2023Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Candice Thomas, Jean Charbonnier, Perceval Coudrain, Maud Vinet
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Publication number: 20230132980Abstract: The present description concerns a method of manufacturing a vapor chamber (300) comprising the following steps: (a) etching, in a first substrate (301), at least one first cavity (303) and at least one channel (313) extending from an upper surface (305) of said first substrate (301), a first end (315) of said channel (313) emerging into said at least one cavity (303); (b) bonding a lower surface of a plate (309) to the upper surface (305) of said first substrate (301), the plate (309) comprising at least one first region made of a ductile material (321) arranged in front of said first end (315) of said channel (313); (c) filling said channel (313) with a cooling fluid (319); and (d) closing said cavity (303) by applying a pressure on said region of ductile material of the plate (309) to obstruct said first end (315) of said channel (313).Type: ApplicationFiled: November 3, 2022Publication date: May 4, 2023Applicant: Commissariat à l'Énergie Atomique et aux Énergies AlternativesInventors: Jean-Philippe Colonna, Perceval Coudrain, Luc Frechette, Quentin Struss
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Publication number: 20220093500Abstract: An integrated structure intended to connect a plurality of semiconductor devices, the integrated structure including a substrate, a first face and a second face, the first face being intended to receive the semiconductor devices, the integrated structure including, at the first face, at least one routing level, the routing level or levels including: at least one first conductor routing track in a conductor material; and at least one first superconductor routing track made from a superconductor material.Type: ApplicationFiled: September 20, 2021Publication date: March 24, 2022Inventors: Candice THOMAS, Jean CHARBONNIER, Perceval COUDRAIN, Maud VINET
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Publication number: 20220093501Abstract: A functional chip includes a substrate including a first face and a second face, the second face of the substrate forming the front face of the functional chip; a first oxide layer on the first face of the substrate; a second oxide layer on the first oxide layer; a first routing level formed on the surface of the second oxide layer in contact with the first oxide layer; a third oxide layer on the second oxide layer wherein a semiconductor component is inserted; a rear face formed by the surface of the third oxide layer opposite the second oxide layer, the rear face including superconductor routing tracks surrounded at least partially by one or more conductor routing tracks, the semiconductor component being connected to the superconductor routing tracks via superconductor vias and the conductor routing tracks of the rear face being connected to the routing level via conductor vias.Type: ApplicationFiled: September 20, 2021Publication date: March 24, 2022Inventors: Candice THOMAS, Jean CHARBONNIER, Perceval COUDRAIN, Maud VINET
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Method of manufacturing a cooling circuit on an integrated circuit chip using a sacrificial material
Patent number: 11152281Abstract: A method for manufacturing a cooling circuit on at least one integrated circuit chip includes producing a cooling circuit on a first face of the chip. Producing the cooling circuit includes forming a definition pattern of the cooling circuit on the first face of the chip, the pattern having at least one layer of a sacrificial material; coating the pattern with at least one resin layer; and at least partially removing the sacrificial material from the pattern so as to open the cooling circuit.Type: GrantFiled: November 6, 2019Date of Patent: October 19, 2021Assignee: Commissariat A L'Energie Atomique et aux Energies AlternativesInventors: Louis-Michel Collin, Jean-Philippe Colonna, Perceval Coudrain, Luc Frechette -
Publication number: 20200144152Abstract: The present invention relates to a method for manufacturing a cooling circuit on at least one integrated circuit chip (1), comprising producing a cooling circuit on a first face of the chip (1), characterised in that the production of the cooling circuit comprises: forming a definition pattern of the cooling circuit (4) on the first face of the chip (1), said pattern comprising at least one layer of a sacrificial material (42); coating (6) said pattern by at least one resin layer; at least partially removing the sacrificial material from said pattern so as to open the cooling circuit (2).Type: ApplicationFiled: November 6, 2019Publication date: May 7, 2020Applicant: Commissariat A L'Energie Atomique et aux Energies AlternativesInventors: Louis-Michel COLLIN, Jean-Philippe COLONNA, Perceval COUDRAIN, Luc FRECHETTE
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Patent number: 10480833Abstract: A heat-transferring device is formed by a stack that includes at least one heat-conducting layer and at least one heat-absorbing layer. The at least one heat-conducting layer has at least one heat-collecting section placed facing a heat source and at least one heat-evacuating section placed facing a heat sink. The at least one heat-absorbing layer includes a phase-change material. One face of the at least one heat-absorbing layer is adjoined to at least one portion of at least one face of the heat-conducting layer.Type: GrantFiled: November 2, 2017Date of Patent: November 19, 2019Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SAInventors: Rafael Augusto Prieto Herrera, Jean-Philippe Colonna, Perceval Coudrain
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Patent number: 9997431Abstract: An electronic device includes a support and a component in the form of an integrated circuit chip having a rear face mounted above a front face of the support and a front face opposite its rear face. A block is provided for at least partially encapsulating the component above the front face of the support. The device also includes at least one thermal dissipation member having a flexible sheet having at least two portions folded onto one another while forming at least one fold between them, these portions facing one another at least partly.Type: GrantFiled: March 7, 2017Date of Patent: June 12, 2018Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA, Commissariat A L'Energie Atomique et aux Energies AlternativesInventors: Rafael Augusto Prieto Herrera, Jean-Philippe Colonna, Perceval Coudrain
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Publication number: 20180142923Abstract: A heat-transferring device is formed by a stack that includes at least one heat-conducting layer and at least one heat-absorbing layer. The at least one heat-conducting layer has at least one heat-collecting section placed facing a heat source and at least one heat-evacuating section placed facing a heat sink. The at least one heat-absorbing layer includes a phase-change material. One face of the at least one heat-absorbing layer is adjoined to at least one portion of at least one face of the heat-conducting layer.Type: ApplicationFiled: November 2, 2017Publication date: May 24, 2018Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SAInventors: Rafael Augusto Prieto Herrera, Jean-Philippe Colonna, Perceval Coudrain
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Patent number: 9870947Abstract: Electronic devices are manufactured using a collective (wafer-scale) fabrication process. Electronic chips are mounted onto one face of a collective substrate wafer. A collective flexible sheet made of a heat-conductive material comprising a layer containing pyrolytic graphite is fixed to extend over a collective region extending over the electronic chips and over the collective substrate wafer between the electronic chips. The collective flexible sheet is then compressed. A dicing operation is then carried out in order to obtain electronic devices each including an electronic chip, a portion of the collective plate and a portion of the collective flexible sheet.Type: GrantFiled: June 26, 2017Date of Patent: January 16, 2018Assignees: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics SA, Commissariat A L'Energie Atomique et aux Energies AlternativesInventors: Didier Campos, Benoit Besancon, Perceval Coudrain, Jean-Philippe Colonna
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Publication number: 20180005889Abstract: Electronic devices are manufactured using a collective (wafer-scale) fabrication process. Electronic chips are mounted onto one face of a collective substrate wafer. A collective flexible sheet made of a heat-conductive material comprising a layer containing pyrolytic graphite is fixed to extend over a collective region extending over the electronic chips and over the collective substrate wafer between the electronic chips. The collective flexible sheet is then compressed. A dicing operation is then carried out in order to obtain electronic devices each including an electronic chip, a portion of the collective plate and a portion of the collective flexible sheet.Type: ApplicationFiled: June 26, 2017Publication date: January 4, 2018Applicants: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics SA, Commissariat A L'Energie Atomique et aux Energies AlternativesInventors: Didier Campos, Benoit Besancon, Perceval Coudrain, Jean-Philippe Colonna
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Publication number: 20170287806Abstract: An electronic device includes a support and a component in the form of an integrated circuit chip having a rear face mounted above a front face of the support and a front face opposite its rear face. A block is provided for at least partially encapsulating the component above the front face of the support. The device also includes at least one thermal dissipation member having a flexible sheet having at least two portions folded onto one another while forming at least one fold between them, these portions facing one another at least partly.Type: ApplicationFiled: March 7, 2017Publication date: October 5, 2017Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA, Commissariat A L'Energie Atomique et aux Energies AlternativesInventors: Rafael Augusto Prieto Herrera, Jean-Philippe Colonna, Perceval Coudrain
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Patent number: 9646914Abstract: A three-dimensional integrated structure includes a first and a second element each having an interconnection part formed by metallization levels encased in an insulating region. The first and second elements are attached to one another by the respective interconnection parts. The first element includes an electrical connection via passing through a substrate. A thermal cooling system includes at least one cavity having a first part located in the insulating region of the interconnection part of the first element and a second part located in the insulating region of the interconnection part of the second element and at least one through channel extending from a rear face of the first element to open into the at least one cavity.Type: GrantFiled: December 3, 2015Date of Patent: May 9, 2017Assignee: STMicroelectronics SAInventors: Pierre Bar, Perceval Coudrain
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Publication number: 20160343638Abstract: A three-dimensional integrated structure includes a first and a second element each having an interconnection part formed by metallization levels encased in an insulating region. The first and second elements are attached to one another by the respective interconnection parts. The first element includes an electrical connection via passing through a substrate. A thermal cooling system includes at least one cavity having a first part located in the insulating region of the interconnection part of the first element and a second part located in the insulating region of the interconnection part of the second element and at least one through channel extending from a rear face of the first element to open into the at least one cavity.Type: ApplicationFiled: December 3, 2015Publication date: November 24, 2016Applicant: STMicroelectronics SAInventors: Pierre Bar, Perceval Coudrain
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Patent number: 9224708Abstract: The invention relates to a method for producing an interconnection pad on a conducting element comprising an upper face and a side wall; the method being executed from a substrate at least the upper face of which is insulating; the conducting element going through at least an insulating portion of the substrate, the method being characterized in that it comprises the sequence of the following steps: a step of embossing the conducting element, a step of forming, above the upper insulating face of the substrate, a stack of layers comprising at least one electrically conducting layer and one electrically resistive layer, a step of partially removing the electrically resistive layer, a step of electrolytic growth on the portion of the electrically conducting layer so as to form at least one interconnection pad on said conducting element.Type: GrantFiled: July 24, 2014Date of Patent: December 29, 2015Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, STMICROELECTRONICS S.A.Inventors: Jean-Philippe Colonna, Perceval Coudrain
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Publication number: 20150028488Abstract: The invention relates to a method for producing an interconnection pad on a conducting element comprising an upper face and a side wall; the method being executed from a substrate at least the upper face of which is insulating; the conducting element going through at least an insulating portion of the substrate, the method being characterized in that it comprises the sequence of the following steps: a step of embossing the conducting element, a step of forming, above the upper insulating face of the substrate, a stack of layers comprising at least one electrically conducting layer and one electrically resistive layer, a step of partially removing the electrically resistive layer, a step of electrolytic growth on the portion of the electrically conducting layer so as to form at least one interconnection pad on said conducting element.Type: ApplicationFiled: July 24, 2014Publication date: January 29, 2015Applicants: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT, STMICROELECTRONICS SAInventors: Jean-Philippe COLONNA, Perceval COUDRAIN
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Patent number: 8828797Abstract: A three-dimensional integrated structure is fabricated by assembling at least two parts together, wherein each part contains at least one metallic line covered with a covering region and having a free side. A cavity is formed in the covering region of each part, that cavity opening onto the metallic line. The two parts are joined together with the free sides facing each other and the cavities in each covering region aligned with each other. The metallic lines are then electrically joined to each other through an electromigration of the metal within at least one of the metallic lines, the electromigrated material filling the aligned cavities.Type: GrantFiled: August 31, 2011Date of Patent: September 9, 2014Assignee: STMicroelectronics SAInventors: Perceval Coudrain, Yacine Felk, Patrick Lamontagne
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Patent number: 8766381Abstract: The integrated circuit comprises a support substrate having opposite first and second main surfaces. A cavity passes through the support substrate and connects the first and second main surfaces. The integrated circuit comprises a device with a mobile element, the mobile element and a pair of associated electrodes of which are included in a cavity. An anchoring node of the mobile element is located at the level of the first main surface. The integrated circuit comprises a first elementary chip arranged at the level of the first main surface and electrically connected to the device with a mobile element.Type: GrantFiled: September 12, 2011Date of Patent: July 1, 2014Assignees: STMicroelectronics SA, STMicroelectronics (Crolles 2) SASInventors: Fabrice Casset, Lionel Cadix, Perceval Coudrain, Alexis Farcy, Laurent-Luc Chapelon, Yacine Felk, Pascal Ancey