Abstract: An integration system and method for the manufacture of radio frequency transmission front-end modules with radio frequency integrated circuit(s) and self-biased magnetic component(s) integrated on a “Wafer Level Packaging”-type technology. This integration makes it possible to design efficient, compact and low-cost front-end modules.

Abstract: A substrate is provided, including: a first layer based on a semiconductive material; a second layer surmounting the first layer; and a plurality of buried vias extending from the second layer over a portion of the first layer, each via of the plurality of buried vias being delimited by a side wall, a bottom wall, and an upper wall opposite the bottom wall, at least one assembly of the plurality of vias forming a pattern repeated along at least one direction of a main extension plane of the first layer and the second layer. A method for manufacturing the substrate is also provided. A method for manufacturing a microelectronic device is also provided.

Abstract: A substrate is provided, including: a first layer based on a semiconductive material; a second layer surmounting the first layer; and a plurality of buried vias extending from the second layer over a portion of the first layer, each via of the plurality of buried vias being delimited by a side wall, a bottom wall, and an upper wall opposite the bottom wall, each via having at least one transverse dimension less than or equal to 30 ?m. A method for manufacturing the substrate is also provided. A method for manufacturing a microelectronic device is also provided.

Abstract: A method of manufacturing a sealed fluid-filled compartment including the following steps: (a) forming at least a first cavity from a first face of a first substrate; (b) positioning a second face of a second substrate opposite the first face of said first substrate; (c) at least partially filling said at least one first cavity with a fluid; (d) bonding said first face of said first substrate to said second face of said second substrate by annealing and simultaneously pressing said first and second substrates together.

Abstract: An integrated structure intended to connect a plurality of semiconductor devices, the integrated structure including a substrate, a first face and a second face, the first face being intended to receive the semiconductor devices, the integrated structure including, at the first face, at least one routing level, the routing level or levels including: at least one first conductor routing track in a conductor material; and at least one first superconductor routing track made from a superconductor material.

Abstract: A SiP-type electronic device, including an electronic chip provided with an electrical interconnection face; a redistribution layer electrically coupled to the electrical interconnection face of the chip; electrical connection elements electrically coupled to the chip by the redistribution layer which is arranged between the chip and the connection elements; a first metal layer arranged on the side of a second face of the chip and secured to this second face; an encapsulation material arranged around the chip, between the redistribution layer and the first metal layer; a second metal layer including a first face secured by direct bonding to the first metal layer; a substrate arranged against a second face of the second metal layer.

Abstract: An integration system and method for the manufacture of radio frequency transmission front-end modules with radio frequency integrated circuit(s) and self-biased magnetic component(s) integrated on a “Wafer Level Packaging”-type technology. This integration makes it possible to design efficient, compact and low-cost front-end modules.

Abstract: A functional chip includes a substrate including a first face and a second face, the second face of the substrate forming the front face of the functional chip; a first oxide layer on the first face of the substrate; a second oxide layer on the first oxide layer; a first routing level formed on the surface of the second oxide layer in contact with the first oxide layer; a third oxide layer on the second oxide layer wherein a semiconductor component is inserted; a rear face formed by the surface of the third oxide layer opposite the second oxide layer, the rear face including superconductor routing tracks surrounded at least partially by one or more conductor routing tracks, the semiconductor component being connected to the superconductor routing tracks via superconductor vias and the conductor routing tracks of the rear face being connected to the routing level via conductor vias.

Abstract: The present description concerns a method of manufacturing a vapor chamber (300) comprising the following steps: (a) etching, in a first substrate (301), at least one first cavity (303) and at least one channel (313) extending from an upper surface (305) of said first substrate (301), a first end (315) of said channel (313) emerging into said at least one cavity (303); (b) bonding a lower surface of a plate (309) to the upper surface (305) of said first substrate (301), the plate (309) comprising at least one first region made of a ductile material (321) arranged in front of said first end (315) of said channel (313); (c) filling said channel (313) with a cooling fluid (319); and (d) closing said cavity (303) by applying a pressure on said region of ductile material of the plate (309) to obstruct said first end (315) of said channel (313).

Abstract: An integrated structure intended to connect a plurality of semiconductor devices, the integrated structure including a substrate, a first face and a second face, the first face being intended to receive the semiconductor devices, the integrated structure including, at the first face, at least one routing level, the routing level or levels including: at least one first conductor routing track in a conductor material; and at least one first superconductor routing track made from a superconductor material.

Abstract: A functional chip includes a substrate including a first face and a second face, the second face of the substrate forming the front face of the functional chip; a first oxide layer on the first face of the substrate; a second oxide layer on the first oxide layer; a first routing level formed on the surface of the second oxide layer in contact with the first oxide layer; a third oxide layer on the second oxide layer wherein a semiconductor component is inserted; a rear face formed by the surface of the third oxide layer opposite the second oxide layer, the rear face including superconductor routing tracks surrounded at least partially by one or more conductor routing tracks, the semiconductor component being connected to the superconductor routing tracks via superconductor vias and the conductor routing tracks of the rear face being connected to the routing level via conductor vias.

Abstract: A method for manufacturing a cooling circuit on at least one integrated circuit chip includes producing a cooling circuit on a first face of the chip. Producing the cooling circuit includes forming a definition pattern of the cooling circuit on the first face of the chip, the pattern having at least one layer of a sacrificial material; coating the pattern with at least one resin layer; and at least partially removing the sacrificial material from the pattern so as to open the cooling circuit.

Abstract: The present invention relates to a method for manufacturing a cooling circuit on at least one integrated circuit chip (1), comprising producing a cooling circuit on a first face of the chip (1), characterised in that the production of the cooling circuit comprises: forming a definition pattern of the cooling circuit (4) on the first face of the chip (1), said pattern comprising at least one layer of a sacrificial material (42); coating (6) said pattern by at least one resin layer; at least partially removing the sacrificial material from said pattern so as to open the cooling circuit (2).

Abstract: A heat-transferring device is formed by a stack that includes at least one heat-conducting layer and at least one heat-absorbing layer. The at least one heat-conducting layer has at least one heat-collecting section placed facing a heat source and at least one heat-evacuating section placed facing a heat sink. The at least one heat-absorbing layer includes a phase-change material. One face of the at least one heat-absorbing layer is adjoined to at least one portion of at least one face of the heat-conducting layer.

Abstract: An electronic device includes a support and a component in the form of an integrated circuit chip having a rear face mounted above a front face of the support and a front face opposite its rear face. A block is provided for at least partially encapsulating the component above the front face of the support. The device also includes at least one thermal dissipation member having a flexible sheet having at least two portions folded onto one another while forming at least one fold between them, these portions facing one another at least partly.

Abstract: A heat-transferring device is formed by a stack that includes at least one heat-conducting layer and at least one heat-absorbing layer. The at least one heat-conducting layer has at least one heat-collecting section placed facing a heat source and at least one heat-evacuating section placed facing a heat sink. The at least one heat-absorbing layer includes a phase-change material. One face of the at least one heat-absorbing layer is adjoined to at least one portion of at least one face of the heat-conducting layer.

Abstract: Electronic devices are manufactured using a collective (wafer-scale) fabrication process. Electronic chips are mounted onto one face of a collective substrate wafer. A collective flexible sheet made of a heat-conductive material comprising a layer containing pyrolytic graphite is fixed to extend over a collective region extending over the electronic chips and over the collective substrate wafer between the electronic chips. The collective flexible sheet is then compressed. A dicing operation is then carried out in order to obtain electronic devices each including an electronic chip, a portion of the collective plate and a portion of the collective flexible sheet.

Abstract: Electronic devices are manufactured using a collective (wafer-scale) fabrication process. Electronic chips are mounted onto one face of a collective substrate wafer. A collective flexible sheet made of a heat-conductive material comprising a layer containing pyrolytic graphite is fixed to extend over a collective region extending over the electronic chips and over the collective substrate wafer between the electronic chips. The collective flexible sheet is then compressed. A dicing operation is then carried out in order to obtain electronic devices each including an electronic chip, a portion of the collective plate and a portion of the collective flexible sheet.

Abstract: An electronic device includes a support and a component in the form of an integrated circuit chip having a rear face mounted above a front face of the support and a front face opposite its rear face. A block is provided for at least partially encapsulating the component above the front face of the support. The device also includes at least one thermal dissipation member having a flexible sheet having at least two portions folded onto one another while forming at least one fold between them, these portions facing one another at least partly.

Abstract: A three-dimensional integrated structure includes a first and a second element each having an interconnection part formed by metallization levels encased in an insulating region. The first and second elements are attached to one another by the respective interconnection parts. The first element includes an electrical connection via passing through a substrate. A thermal cooling system includes at least one cavity having a first part located in the insulating region of the interconnection part of the first element and a second part located in the insulating region of the interconnection part of the second element and at least one through channel extending from a rear face of the first element to open into the at least one cavity.