Patents by Inventor Percy Edgard Neyra

Percy Edgard Neyra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11770071
    Abstract: A method for dynamic enhancement of loop response upon recovery from fault conditions includes detecting a fault condition in response to a programmed output voltage of a Pulse Width Modulation (PWM) converter decreasing below an input voltage of the PWM converter. A peak voltage is sampled at the end of at least one of a plurality of clock cycles of the PWM converter in response to detecting the fault condition, wherein the peak voltage is proportional to a sensed current conducted through a transistor. An error output of an error amplifier is preset to an error value determined by the peak voltage. A PWM driver is controlled with the error value to drive the transistor. An output load is charged to the programmed output voltage with the transistor in response to the input voltage increasing above the programmed output voltage.
    Type: Grant
    Filed: June 17, 2021
    Date of Patent: September 26, 2023
    Assignee: NXP USA, INC.
    Inventors: Percy Edgard Neyra, John Ryan Goodfellow, Ondrej Pauk
  • Publication number: 20210313882
    Abstract: A method for dynamic enhancement of loop response upon recovery from fault conditions includes detecting a fault condition in response to a programmed output voltage of a Pulse Width Modulation (PWM) converter decreasing below an input voltage of the PWM converter. A peak voltage is sampled at the end of at least one of a plurality of clock cycles of the PWM converter in response to detecting the fault condition, wherein the peak voltage is proportional to a sensed current conducted through a transistor. An error output of an error amplifier is preset to an error value determined by the peak voltage. A PWM driver is controlled with the error value to drive the transistor. An output load is charged to the programmed output voltage with the transistor in response to the input voltage increasing above the programmed output voltage.
    Type: Application
    Filed: June 17, 2021
    Publication date: October 7, 2021
    Inventors: Percy Edgard Neyra, John Ryan Goodfellow, Ondrej Pauk
  • Patent number: 11050347
    Abstract: A method for dynamic enhancement of loop response upon recovery from fault conditions includes detecting a fault condition in response to a programmed output voltage of a Pulse Width Modulation (PWM) converter decreasing below an input voltage of the PWM converter. A peak voltage is sampled at the end of at least one of a plurality of clock cycles of the PWM converter in response to detecting the fault condition, wherein the peak voltage is proportional to a sensed current conducted through a transistor. An error output of an error amplifier is preset to an error value determined by the peak voltage. A PWM driver is controlled with the error value to drive the transistor. An output load is charged to the programmed output voltage with the transistor in response to the input voltage increasing above the programmed output voltage.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: June 29, 2021
    Assignee: NXP USA, Inc.
    Inventors: Percy Edgard Neyra, John Ryan Goodfellow, Ondrej Pauk
  • Publication number: 20210006158
    Abstract: A method for dynamic enhancement of loop response upon recovery from fault conditions includes detecting a fault condition in response to a programmed output voltage of a Pulse Width Modulation (PWM) converter decreasing below an input voltage of the PWM converter. A peak voltage is sampled at the end of at least one of a plurality of clock cycles of the PWM converter in response to detecting the fault condition, wherein the peak voltage is proportional to a sensed current conducted through a transistor. An error output of an error amplifier is preset to an error value determined by the peak voltage. A PWM driver is controlled with the error value to drive the transistor. An output load is charged to the programmed output voltage with the transistor in response to the input voltage increasing above the programmed output voltage.
    Type: Application
    Filed: July 1, 2019
    Publication date: January 7, 2021
    Inventors: Percy Edgard Neyra, John Ryan Goodfellow, Ondrej Pauk
  • Patent number: 10218254
    Abstract: Embodiments of a switched-mode power supply and a method for operating a switched-mode power supply involve synchronizing a phase and frequency of an asynchronous controller of the switched-mode power supply with a clock signal of a synchronous controller of the switched-mode power supply while the asynchronous controller is in control of a power stage of the switched-mode power supply, concurrent with synchronizing the phase and frequency of the asynchronous controller with the clock signal of the synchronous controller, presetting a state variable of the synchronous controller while the asynchronous controller is in control of the power stage of the switched-mode power supply, and switching control of the power stage from the asynchronous controller to the synchronous controller after the phase and frequency of the asynchronous controller are synchronized with the clock signal of the synchronous controller and after the state variable of the synchronous controller is preset.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: February 26, 2019
    Assignee: NXP USA, Inc.
    Inventors: Percy Edgard Neyra, John Pigott, John Ryan Goodfellow, Kyle James Wollschlager, Ondrej Pauk, Raviraj Dattatraya Vader