Abstract: A method for forming a CMOS device in a manner so as to avoid dielectric layer undercut during a pre-silicide cleaning step is described. During formation of CMOS device comprising a gate stack on a semiconductor substrate surface, the patterned gate stack including gate dielectric below a conductor with vertical sidewalls, a dielectric layer is formed thereover and over the substrate surfaces. Respective nitride spacer elements overlying the dielectric layer are formed at each vertical sidewall. The dielectric layer on the substrate surface is removed using an etch process such that a portion of the dielectric layer underlying each spacer remains. Then, a nitride layer is deposited over the entire sample (the gate stack, the spacer elements at each gate sidewall, and substrate surfaces) and subsequently removed by an etch process such that only a portion of said nitride film (the “plug”) remains.

Abstract: A method for forming a CMOS device in a manner so as to avoid dielectric layer undercut during a pre-silicide cleaning step is described. During formation of CMOS device comprising a gate stack on a semiconductor substrate surface, the patterned gate stack including gate dielectric below a conductor with vertical sidewalls, a dielectric layer is formed thereover and over the substrate surfaces. Respective nitride spacer elements overlying the dielectric layer are formed at each vertical sidewall. The dielectric layer on the substrate surface is removed using an etch process such that a portion of the dielectric layer underlying each spacer remains. Then, a nitride layer is deposited over the entire sample (the gate stack, the spacer elements at each gate sidewall, and substrate surfaces) and subsequently removed by an etch process such that only a portion of said nitride film (the “plug”) remains.

Abstract: Disclosed is a method and system of forming an integrated circuit transistor having a reduced gate height that forms a laminated structure having a substrate, a gate conductor above the substrate, and at least one sacrificial layer above the gate conductor. The process patterns the laminated structure into at least one gate stack extending from the substrate, forms spacers adjacent to the gate stack, dopes regions of the substrate not protected by the spacers to form source and drain regions adjacent the gate stack, and removes the spacers and the sacrificial layer.

Abstract: A thin film silicon on insulator circuit with a low voltage triggered, surface silicon controlled rectifier (30) for electrostatic damage protection and method is provided. A surface silicon controller rectifier (30) is formed in a thin device layer (130), overlying a buried insulation layer (110) and electrically coupled to a low voltage trigger apparatus (36). In one embodiment, a zener diode is employed as the low voltage trigger apparatus (36), and in another embodiment low voltage trigger apparatus (36) is an n-channel MOSFET.