Patents by Inventor Percy Heger

Percy Heger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140015523
    Abstract: Detecting arcing events in a DC driven semiconductor tool is a challenging process. Various embodiments comprise dedicated sensor devices capable of detecting arcing events by observing the slope of voltage and/or current of a DC power supply line. Using the incorporated interfaces, the sensor could be connected to a computer system. Besides the detector arrangement the unit also provides a method and a corresponding computer program product. Furthermore a simple detection, the unit has the capability of separating the events into its severeness.
    Type: Application
    Filed: July 10, 2012
    Publication date: January 16, 2014
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Jan Rupf, Markus Fischer, Peter Brockhaus, Percy Heger, Norbert Urbansky
  • Patent number: 7354778
    Abstract: A method is provided for determining the end point during cleaning etching of processing chambers by means of plasma etching, which is used for carrying out coating or etching processes during the manufacture of semiconductor components. The invention provides a method for effectively and reliably determining the end point during cleaning etching of processing chambers. The end point is determined by monitoring the DC bias voltage on the plasma generator which is used for the plasma cleaning etching in the processing chamber in an evaluation unit. The plasma cleaning etching process is terminated by stopping the supply of the process gases in the gas supply unit and by switching off the plasma generator upon reaching a predetermined DC bias voltage value which corresponds to completion of the cleaning etching process.
    Type: Grant
    Filed: September 5, 2003
    Date of Patent: April 8, 2008
    Assignee: Infineon Technologies AG
    Inventors: Percy Heger, Tobias Hoerning, Ralf Otto
  • Patent number: 7018781
    Abstract: Disclosed is a method for fabricating a contract hole plane in a memory module with an arrangement of memory cells each having a selection transistor. The methods can be utilized during the production of dynamic random access memory (DRAM) modules.
    Type: Grant
    Filed: March 29, 2004
    Date of Patent: March 28, 2006
    Assignee: Infineon Technologies, AG
    Inventors: Hans-Georg Fröhlich, Oliver Genz, Werner Graf, Stefan Gruss, Matthias Handke, Percy Heger, Lars Heineck, Antje Laessig, Alexander Reb, Kristin Schupke, Momtchil Stavrev, Mirko Vogt
  • Publication number: 20050003308
    Abstract: In order to fabricate a contact hole plane in a memory module with an arrangement of memory cells each having a selection transistor, on a semiconductor substrate with an arrangement of mutually adjacent gate electrode tracks on the semiconductor surface, an insulator layer is formed on the semiconductor surface and a sacrificial layer is subsequently formed on the insulator layer, then material plugs are produced on the sacrificial layer for the purpose of defining contact openings between the mutually adjacent gate electrode tracks, the sacrificial layer is etched to form material plugs with the underlying sacrificial layer blocks, after the production of the vitreous layer with uncovering of the sacrificial layer blocks above the contact openings between the mutually adjacent gate electrode tracks, an essentially planar surface being formed, then the sacrificial layer material is etched out from the vitreous layer and the uncovered insulator material is removed above the contact openings on the semiconduct
    Type: Application
    Filed: March 29, 2004
    Publication date: January 6, 2005
    Applicant: Infineon Technologies AG
    Inventors: Hans-Georg Frohlich, Oliver Genz, Werner Graf, Stefan Gruss, Matthias Handke, Percy Heger, Lars Heineck, Antje Laessig, Alexander Reb, Kristin Schupke, Momtchil Stavrev, Mirko Vogt
  • Publication number: 20040087170
    Abstract: A method is provided for determining the end point during cleaning etching of processing chambers by means of plasma etching, which is used for carrying out coating or etching processes during the manufacture of semiconductor components. The invention provides a method for effectively and reliably determining the end point during cleaning etching of processing chambers. The end point is determined by monitoring the DC bias voltage on the plasma generator which is used for the plasma cleaning etching in the processing chamber in an evaluation unit. The plasma cleaning etching process is terminated by stopping the supply of the process gases in the gas supply unit and by switching off the plasma generator upon reaching a predetermined DC bias voltage value which corresponds to completion of the cleaning etching process.
    Type: Application
    Filed: September 5, 2003
    Publication date: May 6, 2004
    Inventors: Percy Heger, Tobias Hoernig, Ralf Otto