Abstract: A testing method and apparatus for improving an efficiency of a post-production connectivity test of a bus coupling a semiconductor device to a bus connector each integrated on a system board. The method includes applying a special test fixture to the connector in lieu of a device designed to be operated by the particular bus. The test fixtures includes a plurality of memories having inputs and outputs connected to one of the conductors of the bus. By applying known patterns of signals to the memories and reading the outputs of the memories, connectivity of the bus is tested without operating the bus.

Abstract: A data processing system having a processor capable of initiating a request for a burst of data transfer and a memory. A memory controller is connected to the processor and to the memory. The controller includes a burst count register having a value stored therein representative of the maximum number of data transfers allowed per burst. Also in the memory controller is a column latch/counter having stored therein a value representative of a column latch address. The column latch/counter is capable of incrementing the address. Finally, included in the memory controller is a programmable mask for specifying bits in the column latch/counter to be compared to corresponding bits in the burst count register.

Abstract: A method of minimizing memory access time on a memory with multiplexed address inputs between data stored in locations in memory in the same row but in different columns. First data is accessed at a predetermined column and row location. The predetermined row location of the first data is then recorded. The location of second data is then recorded. Then the locations of the first and second data are compared. A row compare signal is generated if the row value of both first and second data are identical. Only the column address is varied in response to the row compare signal.

Abstract: A method and apparatus for testing operation of an n-bit counter with carry inputs in an electronic system. The n-bit counter is divided into a high section and a low section. An external carry is forced to the lowest significant bit of the high section. All states of both sections of the counter are clocked, each state of each of the sections being clocked simultaneously with a corresponding state of the other of the sections. The natural carry is selected so that, at the next clock cycle, when the low section is set at the highest count, the highest significant bit of the low section is carried to the lowest significant bit of the high section.