Abstract: The invention provides a new linked structure for a buffer controller and management method thereof. The allocation and release actions of buffer memory can be more effectively processed when the buffer controller processes data packets. The linked structure enables the link node of the first buffer register to point to the last buffer register. The link node of the last buffer register points to the second buffer register. Each of the link nodes of the rest buffers points to the next buffer register in order until the last buffer register. This structure can effectively release the buffer registers in the used linked list to a free list.

Abstract: The invention provides a new linked structure for a buffer controller and management method thereof. The allocation and release actions of buffer memory can be more effectively processed when the buffer controller processes data packets. The linked structure enables the link node of the first buffer register to point to the last buffer register. The link node of the last buffer register points to the second buffer register. Each of the link nodes of the rest buffers points to the next buffer register in order until the last buffer register. This structure can effectively release the buffer registers in the used linked list to a free list.

Abstract: The invention provides a new linked structure for a buffer controller and management method thereof. The allocation and release actions of buffer memory can be more effectively processed when the buffer controller processes data packets. The linked structure enables the link node of the first buffer register to point to the last buffer register. The link node of the last buffer register points to the second buffer register. Each of the link nodes of the rest buffers points to the next buffer register in order until the last buffer register. This structure can effectively release the buffer registers in the used linked list to a free list.

Abstract: In a method for testing an embedded phase-locked loop (PLL) circuit, a first clock signal is provided to an embedded phase-locked loop (PLL) circuit to be tested. A PLL clock signal of a first frequency is generated by the embedded PLL in response to the first clock signal. The PLL clock signal of the first frequency is sampled with a second clock signal of a second frequency to generate a first sampled signal, wherein the second frequency is different from the first frequency but has a first correlation with the first frequency so that the first sampled signal toggles at a predetermined frequency when the embedded PLL circuit is in a normal operation condition. The embedded PLL circuit is determined to be in an abnormal operation condition if the first sampled signal does not toggle at said predetermined frequency.

Abstract: A data packet transmission method for use in a network switch is disclosed. The network switch includes a plurality of connection ports for tranceiving a data packet therefrom, a tag substitution rule table defining a tag substitution rule, a VLAN reference table defining the correlation of a tagging rule with a VLAN information of the data packet, a multicast reference table defining the relationship of a multicast port mask with a multicasting information of the data packet, and a tag determination device. The tag determination device transmits the data packet to destination ports according to the multicast port mask, determines the VLAN tag(s) to be affixed to the data packet for the destination ports according to the tag substitution rule, and optionally removes the VLAN tag for the destination ports according to the tagging rule.

Abstract: In a method for testing an embedded phase-locked loop (PLL) circuit, a first clock signal is provided to an embedded phase-locked loop (PLL) circuit to be tested. A PLL clock signal of a first frequency is generated by the embedded PLL in response to the first clock signal. The PLL clock signal of the first frequency is sampled with a second clock signal of a second frequency to generate a first sampled signal, wherein the second frequency is different from the first frequency but has a first correlation with the first frequency so that the first sampled signal toggles at a predetermined frequency when the embedded PLL circuit is in a normal operation condition. The embedded PLL circuit is determined to be in an abnormal operation condition if the first sampled signal does not toggle at said predetermined frequency.

Abstract: A method and a device for testing an embedded phase-locked loop (PLL) circuit are disclosed. A first clock signal of a first frequency is provided to an embedded phase-locked loop (PLL) circuit to be tested by a tester, so as to generate a PLL clock signal by the embedded PLL circuit in response to the first clock signal of the first frequency. The PLL clock signal is inputted to a test circuit along with a second clock signal of a second frequency. Then, the PLL clock signal is sampled with the second clock signal of the second frequency to generate a first sampled signal. The second frequency has a first correlation with the first frequency. Whether the embedded PLL circuit is in a normal operation condition is determined according to the first sampled signal.

Abstract: The invention provides a new linked structure for a buffer controller and management method thereof. The allocation and release actions of buffer memory can be more effectively processed when the buffer controller processes data packets. The linked structure enables the link node of the first buffer register to point to the last buffer register. The link node of the last buffer register points to the second buffer register. Each of the link nodes of the rest buffers points to the next buffer register in order until the last buffer register. This structure can effectively release the buffer registers in the used linked list to a free list.

Abstract: The invention provides a new linked structure for a buffer controller and management method thereof The allocation and release actions of buffer memory can be more effectively processed when the buffer controller processes data packets. The linked structure enables the link node of the first buffer register to point to the last buffer register. The link node of the last buffer register points to the second buffer register. Each of the link nodes of the rest buffers points to the next buffer register in order until the last buffer register. This structure can effectively release the buffer registers in the used linked list to a free list.

Abstract: The invention provides a new linked structure for a buffer controller and management method thereof. The allocation and release actions of buffer memory can be more effectively processed when the buffer controller processes data packets. The linked structure enables the link node of the first buffer register to point to the last buffer register. The link node of the last buffer register points to the second buffer register. Each of the link nodes of the rest buffers points to the next buffer register in order until the last buffer register. This structure can effectively release the buffer registers in the used linked list to a free list.

Abstract: A method and a device for testing an embedded phase-locked loop (PLL) circuit are disclosed. A first clock signal of a first frequency is provided to an embedded phase-locked loop (PLL) circuit to be tested by a tester, so as to generate a PLL clock signal by the embedded PLL circuit in response to the first clock signal of the first frequency. The PLL clock signal is inputted to a test circuit along with a second clock signal of a second frequency. Then, the PLL clock signal is sampled with the second clock signal of the second frequency to generate a first sampled signal. The second frequency has a first correlation with the first frequency. Whether the embedded PLL circuit is in a normal operation condition is determined according to the first sampled signal.

Abstract: A data packet transmission method for use in a network switch is disclosed. The network switch includes a plurality of connection ports for tranceiving a data packet therefrom, a tag substitution rule table defining a tag substitution rule, a VLAN reference table defining the correlation of a tagging rule with a VLAN information of the data packet, a multicast reference table defining the relationship of a multicast port mask with a multicasting information of the data packet, and a tag determination device. The tag determination device transmits the data packet to destination ports according to the multicast port mask, determines the VLAN tag(s) to be affixed to the data packet for the destination ports according to the tag substitution rule, and optionally removes the VLAN tag for the destination ports according to the tagging rule.