Abstract: The boundary between the P type silicon base and N+ buffer layer of an IGBT is intentionally damaged, as by a germanium implant, to create well defined and located damage sites for reducing lifetime in the silicon.

Abstract: The boundary between the P type silicon base and N.sup.+ buffer layer of an IGBT is intentionally damaged, as by a germanium implant, to create well defined and located damage sites for reducing lifetime in the silicon.

Abstract: A vertical conduction Schottky device having a reverse voltage rating in excess of 400 volts uses an aluminum barrier metal in contact with an N.sup.- epitaxial silicon surface. A diffused P.sup.+ guard ring surrounds the barrier metal contact and is spaced therefrom by a small gap which is fully depleted at a low reverse voltage to connect the ring to the barrier contact under reverse voltage conditions. Lifetime killing is used for the body of the diode.

Abstract: The safe operating area can be increased and the die area can be decreased for a monolithic Darlington circuit employing an MOS input transistor and bipolar output transistor by subdividing the bipolar transistor into a multiplicity of rectangular spaced apart bipolar device regions, each of which is surrounded by an annular shaped MOS device region. The source and channel of the MOS devices are formed in an extension of the base of the bipolar devices. The substrate serves as a common collector for all the bipolar device regions and as a common drain for all the MOS device regions. The gate electrode, which runs over the interstices between the parallel spaced apart bipolar device areas is covered by an insulator so that the emitter metallization may extend substantially over the entire upper surface of the die. A more compact layout and better thermal coupling between the MOS and bipolar devices are obtained. These features reduce the total die area and improve the thermal stability of the circuit.

Abstract: A bipolar power transistor with improved power dissipation capability. The device is designed to reduce the current crowding that obtains at the edge of a relatively wide emitter because of the debiasing effect of the voltage drop in the base region beneath that emitter. In a preferred embodiment, current crowding is reduced by sub-dividing a typical emitter finger into a central emitting region flanked by two peripheral emitting regions separated from the central region by a resistive portion. The resistive portions are desirably of the same conductivity type as the emitter; this design permits the use of relatively coarse geometries compatible with high yield.