Abstract: An integrated circuit includes an array of resistive non-volatile memory cells having a plurality of word lines, a plurality of bit lines, and a plurality of source lines. The integrated circuit includes a sense amplifier coupled to a first bit line of the plurality of bit lines and a corresponding first source line of the plurality of source lines. When a memory cell coupled to the first bit line is selected for a read operation, the sense amplifier is configured to, during a calibration phase of the read operation, store a first voltage representative of a leakage current on the first source line. The sense amplifier is also configured to, during a sense phase of the read operation, apply the stored first voltage to the first bit line and provide a first sense amplifier output indicative of a logic state of the selected memory cell.

Abstract: An integrated circuit includes an array of resistive non-volatile memory cells having a plurality of word lines, a plurality of bit lines, and a plurality of source lines. The integrated circuit includes a sense amplifier coupled to a first bit line of the plurality of bit lines and a corresponding first source line of the plurality of source lines. When a memory cell coupled to the first bit line is selected for a read operation, the sense amplifier is configured to, during a calibration phase of the read operation, store a first voltage representative of a leakage current on the first source line. The sense amplifier is also configured to, during a sense phase of the read operation, apply the stored first voltage to the first bit line and provide a first sense amplifier output indicative of a logic state of the selected memory cell.

Abstract: A semiconductor device includes an array of memory cells, and a reference voltage generation circuit including a first set of reference memory cells coupled to a first bit line, a second set of reference memory cells coupled to a second bit line, a first capacitor having a first terminal coupled to the first bit line, and a second terminal, a second capacitor having a first terminal coupled to the second terminal of the first capacitor at a first node and a second terminal coupled to the second bit line, an amplifier including a first input selectively coupled to the first node and a second input coupled to an output of the amplifier that provides reference voltage used by sense amplifiers, and a third capacitor including a first terminal coupled to the output of the amplifier and a second terminal coupled to a first supply voltage.

Abstract: A memory includes a bit cell array including a plurality of word lines and address decode circuitry having an output to provide a predecode value. The address decode circuitry includes a first plurality of transistors having a first gate oxide thickness. The memory further includes word line driver circuitry having an input coupled to the output of the address decode circuitry and a plurality of outputs, each output coupled to a corresponding word line of the plurality of word lines. The word line driver includes a second plurality of transistors having a second gate oxide thickness greater than the first gate oxide thickness. A method of operating the memory also is provided.

Abstract: In one form a memory and method thereof has a memory array having a plurality of columns of bit lines and a plurality of intersecting rows of word lines. Control circuitry is coupled to the memory array for successively accessing predetermined bit locations in the memory array during successive memory cycles. The control circuitry senses data within the memory array at a beginning of a predetermined memory cycle. Timing of the memory cycle is determined from a single external clock edge of a memory system clock. During a single memory cycle the memory initially performs the function of sensing followed by at least the functions of precharging the bit lines, addressing and developing a signal to be sensed. In one form each of the successive memory cycles is a period of time of no more than a single period of the memory system clock.

Abstract: A semiconductor topography (10) is provided which includes a semiconductor-on-insulator (SOI) substrate having a conductive line (16) arranged within an insulating layer (22) of the SOI substrate. A method for forming an SOI substrate with such a configuration includes forming a first conductive line (16) within an insulating layer (22) arranged above a wafer substrate (12) and forming a silicon layer (24) upon surfaces of the first conductive line and the insulating layer. A further method is provided which includes the formation of a transistor gate (28) upon an SOI substrate having a conductive line (16) embedded therein and implanting dopants within the semiconductor topography to form source and drain regions (30) within an upper semiconductor layer (24) of the SOI substrate such that an underside of one of the source and drain regions is in contact with the conductive line.

Abstract: An integrated circuit memory includes a plurality of memory cells, where each of the plurality of memory cells comprises a first storage node and a second storage node. Each of the plurality of memory cells comprises a transistor coupled between the first and second storage nodes and responsive to an equalization signal. An equalization control circuit provides the equalization signal to selected memory cells of the plurality of memory cells. The equalization control circuit is for equalizing a voltage between the first and second storage nodes to enable to a write operation of the selected memory cells. During the write operation a data signal is provided to a first bit line that swings between a logic high voltage equal to a power supply voltage and a logic low voltage equal to ground potential. The transistor and the equalization control circuit enables reliable memory operation at low power supply voltages.

Abstract: An impedance matching between two integrated circuits is achieved using an impedance measuring circuit in the integrated circuit that contains an impedance-programmable output buffer (IPOB) that is to have its output impedance changed. The impedance measuring device is directly connected to the output of the IPOB so that it is detecting the same impedance that the IPOB will drive and thereby avoids the errors of measuring the resistance of a device that imperfectly models the actual impedance. The impedance measuring device is preferably an analog to digital (A/D) converter that provides a digital output relative to the voltage present on the same terminal as the output of the IPOB. By having the A/D converter on the same integrated circuit as the IPOB, communications difficulties between the A/D converter and the IPOB are minimal.

Abstract: A memory (10) has a memory array (12), a charge pump (18), a voltage regulator (20), a refresh control circuit (16), and a refresh counter (22). The charge pump (18) provides a substrate bias to the memory array (12). The voltage regulator (20) provides a pump enable signal for maintaining a voltage level of the substrate bias within upper and lower limits. The refresh control circuit (16) controls refresh operations. The refresh counter (22) is coupled to receive the pump enable signal, and in response, provides a refresh timing signal to the refresh control circuit (16) to control a refresh rate of the memory array (12). A programmable fuse circuit (26) is provided to program the refresh rate using the counter (22). The programmable fuse circuit (26) may be programmed during wafer probe testing or board level burn-in. A built-in self test (BIST) circuit (24) may be included to facilitate testing.

Abstract: A memory (10) has a plurality of memory cells, a serial address port (47) for receiving a low voltage high frequency differential address signal, and a serial input/output data port (52, 54) for receiving a high frequency low voltage differential data signal. The memory (10) can operate in one of two different modes, a normal mode and a cache line mode. In cache line mode, the memory can access an entire cache line from a single address. A fully hidden refresh mode allows for timely refresh operations while operating in cache line mode. Data is stored in the memory array (14) by interleaving in multiple sub-arrays (15, 17). During a hidden refresh mode of operation, one sub-array (15) is accessed while another sub-array (17) is refreshed. Two or more of the memories (10) may be chained together to provide a high speed low power memory system.

Abstract: A memory (10) has a plurality of memory cells, a serial address port (47) for receiving a low voltage high frequency differential address signal, and a serial input/output data port (52, 54) for receiving a high frequency low voltage differential data signal. The memory (10) can operate in one of two different modes, a normal mode and a cache line mode. In cache line mode, the memory can access an entire cache line from a single address. A fully hidden refresh mode allows for timely refresh operations while operating in cache line mode. Data is stored in the memory array (14) by interleaving in multiple sub-arrays (15, 17). During a hidden refresh mode of operation, one sub-array (15) is accessed while another sub-array (17) is refreshed. Two or more of the memories (10) may be chained together to provide a high speed low power memory system.

Abstract: A memory (10) has a plurality of memory cells, a serial address port (47) for receiving a low voltage high frequency differential address signal, and a serial input/output data port (52, 54) for receiving a high frequency low voltage differential data signal. The memory (10) can operate in one of two different modes, a normal mode and a cache line mode. In cache line mode, the memory can access an entire cache line from a single address. A fully hidden refresh mode allows for timely refresh operations while operating in cache line mode. Data is stored in the memory array (14) by interleaving in multiple sub-arrays (15, 17). During a hidden refresh mode of operation, one sub-array (15) is accessed while another sub-array (17) is refreshed. Two or more of the memories (10) may be chained together to provide a high speed low power memory system.

Abstract: An inductive device (105) is formed above a substrate (225) having a conductive coil formed around a core (109). The coil comprises segments formed from a first plurality of bond wires (113) and a second plurality of bond wires (111). The first plurality of bond wires (113) extends between the core (109) and the substrate (225). Each of the first plurality of bond wires is coupled to two of a plurality of wire bond pads (117, 116). The second plurality of bond wires (111) extends over the core (109) and is coupled between two of the plurality of wire bond pads (117, 119). A shield (141) includes a portion that is positioned between the core (109) and the substrate (225).

Abstract: An integrated circuit with reduced size through improved power supply distribution. A bonding pad supplies V.sub.SS to an integrated circuit memory, which is distributed through a plurality of power supply lines in a first metal layer and a plurality of grid lines in a second metal layer intersecting at right angles. The plurality of grid lines are placed in unused spaced in the second metal layer and are coupled to the power supply lines in the first metal layer. Together the grid lines and the power supply lines provide an improved power supply by lowering the impedance from a point on the integrated circuit to V.sub.SS supplied on the bonding pad. While this technique is ideally suited to memory devices because of the repetitive nature of blocks of memory cells, other types of integrated circuits can also utilize such a power supply distribution technique.