Abstract: A methodology for capturing analog information, such as from an analog sensor, including converting the analog information to a train of pulses, representing the analog information as the number of pulses in the pulse train. This pulse count data can be communicated to a processor configured to count the pulses in the pulse train, and convert this pulse count data into digital data corresponding to the analog information. An example embodiment uses a DAC/comparator to convert the analog information (such as a sensor reading) into a pulse train derived from a DAC count (such as can be generated by a DAC counter from an input DAC clock) that is compared with an analog magnitude (analog information), such that the DAC count, which can be represented by a number of DAC clock pulses, provides the pulse train (pulse count data) that corresponds to the analog information.

Abstract: A methodology for capturing analog information, such as from an analog sensor, including converting the analog information to a train of pulses, representing the analog information as the number of pulses in the pulse train. This pulse count data can be communicated to a processor configured to count the pulses in the pulse train, and convert this pulse count data into digital data corresponding to the analog information. An example embodiment uses a DAC/comparator to convert the analog information (such as a sensor reading) into a pulse train derived from a DAC count (such as can be generated by a DAC counter from an input DAC clock) that is compared with an analog magnitude (analog information), such that the DAC count, which can be represented by a number of DAC clock pulses, provides the pulse train (pulse count data) that corresponds to the analog information.

Abstract: A resistor-programmable device generates pulses counted by a counter. The counter's output controls a drive signal generator, such as an adjustable current source. The drive signal generator generates a drive signal (such as a current), which leads to the creation of a sense signal (such as a voltage) using a resistance. The resistance can have one of a set of specified values or fall within one of a set of specified windows. The resistor-programmable device can convert the resistance value into a digital value, which can be used to set a sensor trip point threshold or some other parameter. The digital or parameter value is independent of changes in the resistance that are within a specified tolerance. For instance, the same parameter value could be selected even when the resistance varies within some tolerance (such as 1%) as the resistor-programmable device can determine the window in which the resistance falls.

Abstract: A temperature-sensor circuit is provided. The temperature-sensor circuit may be configured such that an output of the temperature-sensor circuit trips when a specified temperature is reached. The temperature-sensor circuit may also be configured to trigger hysteresis if the specified temperature is reached. Additionally, the temperature-sensor circuit may be configured for powering up with hysteresis disabled. However, after the completion of a settling period, the hysteresis is enabled for triggering based on the temperature.

Abstract: A resistor-programmable device generates pulses counted by a counter. The counter's output controls a drive signal generator, such as an adjustable current source. The drive signal generator generates a drive signal (such as a current), which leads to the creation of a sense signal (such as a voltage) using a resistance. The resistance can have one of a set of specified values or fall within one of a set of specified windows. The resistor-programmable device can convert the resistance value into a digital value, which can be used to set a sensor trip point threshold or some other parameter. The digital or parameter value is independent of changes in the resistance that are within a specified tolerance. For instance, the same parameter value could be selected even when the resistance varies within some tolerance (such as 1%) as the resistor-programmable device can determine the window in which the resistance falls.

Abstract: The conventional cascode circuit can be improved by adding another transistor in series. The added transistor may use the body effect to reduce supply voltage variations across the cascode transistor as the supply voltage varies. The added transistor reduces impact ionization in the cascode transistor.

Abstract: A thermostat circuit is arranged for dual purpose operation to save pins in a small package. The circuit includes a temperature sensor circuit, a trip-point reference circuit, a switching circuit, an amplifier circuit, and a comparator circuit. The trip-point reference circuit provides a reference voltage that corresponds to a desired trip-point level. The temperature sensor circuit provides a sense voltage that corresponds to temperature. During a normal operating mode the sense voltage is coupled to the input of the amplifier circuit via the switching circuit, while during a test mode the reference voltage is coupled to an input of the amplifier circuit. The amplifier circuit buffers a voltage to one output pin. The comparator circuit compares the reference voltage to the sense voltage to provide a trip-point detection voltage for another output pin. An input pin is provided for selection of either a test mode or a non-test mode.

Abstract: The conventional cascode circuit can be improved by adding another transistor in series. The added transistor may use the body effect to reduce supply voltage variations across the cascode transistor as the supply voltage varies. The added transistor reduces impact ionization in the cascode transistor.

Abstract: A power-on detection circuit is arranged to cooperate with a thermal-voltage generator to determine when predictable circuit operation is achieved. The power-on detection circuit includes a comparator circuit and an inverter circuit. A power-on reset (POR) signal is generated by the inverter circuit, which evaluate an output of the comparator circuit. The comparator circuit includes a differential pair arrangement that is imbalanced with a resistor. The differential pair in the comparator circuit is arranged to determine when the thermal voltage has reached a desired target level by evaluating two points within the thermal-voltage generator circuit. The comparator circuit can have a target level that is below 100% of full operation to improve reliability.

Abstract: A start-up circuit includes a long channel current generator, a subtracting reference current generator, and a gain scaling current mirror-circuit. The long channel current generator circuit uses a long channel transistor circuit that simulates a high value resistor to provide a low-level current. The low-level current is sensed by the subtracting reference current generator to provide a reference current that tracks the low-level current until a diverting current is activated, where the diverting current is subtracted from the reference current such that the reference current increases at a slower rate than the low-level current for increasing supply voltages. The gain scaling current mirror-circuit generates the start-up current as a gain scaled version of the reference current. Once the bias generator circuit is active, a stop-current can be used to shut down the gain scaling current mirror-circuit to conserve current.

Abstract: An op amp is arranged for low-voltage, rail-to-rail operation with a class AB output. The op amp includes a transconductance input stage, a folded cascode middle stage that includes a split cascode, a high-side driver, a low-side driver, a sampling circuit, and a split-cascode bias circuit. The split cascode includes two cascode transistors with their sources coupled to each other. Also, the sampling circuit that is arranged to sample the high-side driver current and the low-side sample current. The split cascode bias current is arranged to compare the sample current with a reference current, and to provide bias voltages to the gates of the two cascode transistors in the split cascode.

Abstract: The present invention controls a thermostat trip point using a resistor-to-digital converter. Generally, the value of an external resistor is measured and converted to a digital code equivalent. The digital code drives a DAC (Digital-to-Analog Converter) which sets the trip point for the thermostat. The tolerance of the external resistor(s) does not contribute to the tolerance of the trip point.

Abstract: The present invention provides a temperature sensor that has high sensitivity and operates in a wide range of temperatures and VDD levels. The temperature sensor may be tailored to the application according to the conditions of temperature and VDD. The temperature sensor comprises five PNP junctions in series. The temperature sensor includes a switch that is configured to block out a predetermined number of the junctions. For example, two junctions may be blocked out. Depending on the state of the switch, the temperature sensor either blocks out a predetermined number of the junctions or operates with all of the junctions active. Blocking out the number of active junctions reduces the sensitivity of the temperature sensor for applications at low temperature and low VDD. The switch may be controlled automatically, or the switch may be hardwired. When the switch is adjusted automatically, a circuit could adjust the switch in response to the temperature information and Vdd conditions.

Abstract: The present invention is directed at a thermostat using a clock burst to control a temperature trip point without the use of an external resistor. A clock burst is applied to a clock input pin from which a counter is used to count the number of pulses. The output of the counter is used to drive a DAC that sets the trip point. No external resistor is needed. This trip point provides a low pin count, flexibility, and high accuracy.

Abstract: A drain-source voltage regulator in a VPTAT generator operates with a lower minimum Vdd and provides a regulated current-mirror voltage. The minimum Vdd can be expressed as Vdd_min=Vdsat_cs+Vdsat_amp+VGS_pmir. Regulation of the current-mirror voltage is achieved by using a common-gate configuration to generate a low-voltage reference. The low-voltage reference is generated inside a regulated feedback loop that includes the VPTAT generator. The current-mirror voltage, which is outside the loop, is indirectly regulated. The current-mirror voltage can be regulated within a voltage range that spans from tens of millivolts to hundreds of millivolts.

Abstract: The present invention is directed at using digital inputs in addition to an external resistor to set the trip point for a thermostat. The digital inputs are used to select a voltage (temperature) range. The value of the external resistor is used to select the specific trip point within the selected range. Since the voltage drop across the resistor is smaller than prior art methods, the tolerance of the resistor is also smaller in terms of voltage or temperature. This results in the trip point for the chip having a tighter tolerance. According to different embodiments, the digital inputs may be actively controlled or hardwired.

Abstract: The operating temperature range for a vertical PNP transistor can be extended by applying cancellation techniques. The vertical PNP generates a first leakage current from the base-collector region. Another vertical PNP transistor is configured to generate a second leakage current, which is coupled to a current-mirror circuit. The output of the current-mirror circuit is configured to provide a cancellation effect on the first leakage current. The current-mirror circuit and vertical PNP may be configured such that the first leakage current is cancelled in a judicious amount, whereby the effects of leakage current and flare-out in the vertical PNP transistor are minimized or cancelled. The cancellation technique is applicable to temperature sensor circuits, thermal voltage generators, and bandgap circuits.

Abstract: A system and method for reading memory elements (e.g., PROMs). The system includes memory elements, a write circuit, and a read circuit. The write circuit is configured to store a charge on one of the memory elements representing a data value. The read circuit is configured to continually detect the charge stored on the memory element and to continually translate the charge into a logic value indicative of the data value when the system is powered on. The read circuit includes a current steering circuit and a detection and translation circuit. The current steering circuit may include a current source coupled to a differential pair, which direct the flow of a current through the memory system based on the stored charge. The detection and translation circuit may include three mirrors, which are configured to detect the current and output the logic value at one of two rails.

Abstract: A method and apparatus is provided that combines bandgap trim, temperature sensor trim, comparator offset trim, and the setting of the temperature trip point. A comparator compares a bandgap reference voltage and temperature sensor voltage and trips the circuit when the temperature voltage is less than the bandgap reference voltage. The temperature voltage is combined with a compensating voltage to trim the circuit and set trip point. A method is provided to adjust the compensating voltage until the circuit trips at the any desired temperature.

Abstract: A segmented digital-to-analog converter circuit employs a tri-level technique to provide an output current in response to a bit code. DAC slice circuits are activated in unary fashion in response to their respective control signal, which are provided by a decoder circuit in response to the high-order bits. Each DAC slice circuit provides a binary weighted current to a summing node in response to the middle-order bits. One of the DAC slice circuits is selected to direct a portion of its total current to the input of a DAC_LOW circuit, where the input current is divided to provide a divided current to the summing node in response to the low-order bits. At certain code transitions a different DAC slice circuit is selected to provide the input current, and the previously selected DAC slice circuit redirects its total current to the summing node such that differential non-linearity errors are minimized.