Patents by Inventor Perry V. Lea
Perry V. Lea has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11894045Abstract: An example apparatus includes a processing in memory (PIM) capable device having an array of memory cells and sensing circuitry coupled to the array. The PIM capable includes a row address strobe (RAS) component selectably coupled to the array. The RAS component is configured to select, retrieve a data value from, and input a data value to a specific row in the array. The PIM capable device also includes a RAS manager selectably coupled to the RAS component. The RAS manager is configured to coordinate timing of a sequence of compute sub-operations performed using the RAS component. The apparatus also includes a source external to the PIM capable device. The RAS manager is configured to receive instructions from the source to control timing of performance of a compute operation using the sensing circuitry.Type: GrantFiled: March 14, 2022Date of Patent: February 6, 2024Inventors: Perry V. Lea, Timothy P. Finkbeiner
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Publication number: 20230401158Abstract: An example memory array page table walk can include using an array of memory cells configured to store a page table. The page table walk can include using sensing circuitry coupled to the array. The page table walk can include using a controller coupled to the array. The controller can be configured to operate the sensing circuitry to determine a physical address of a portion of data by accessing the page table in the array of memory cells. The controller can be configured to operate the sensing circuitry to cause storing of the portion of data in a buffer.Type: ApplicationFiled: May 30, 2023Publication date: December 14, 2023Inventor: Perry V. Lea
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Publication number: 20230393786Abstract: Apparatuses and methods are provided for in-memory operations. An example apparatus includes a PIM capable device having an array of memory cells and sensing circuitry coupled to the array, where the sensing circuitry includes a sense amplifier and a compute component. The PIM capable device includes timing circuitry selectably coupled to the sensing circuitry. The timing circuitry is configured to control timing of performance of operations performed using the sensing circuitry. The PIM capable device also includes a sequencer selectably coupled to the timing circuitry. The sequencer is configured to coordinate compute operations. The apparatus also includes a source external to the PIM capable device. The sequencer is configured to receive a command instruction set from the source to initiate performance of a compute operation.Type: ApplicationFiled: June 8, 2023Publication date: December 7, 2023Inventors: Perry V. Lea, Timothy P. Finkbeiner
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Publication number: 20230386550Abstract: The present disclosure includes apparatuses and methods for performing operations by a memory device in a self-refresh state. An example includes an array of memory cells and a controller coupled to the array of memory cells. The controller is configured to direct performance of compute operations on data stored in the array when the array is in a self-refresh state.Type: ApplicationFiled: May 26, 2023Publication date: November 30, 2023Inventors: Perry V. Lea, Glen E. Hush
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Patent number: 11769053Abstract: The present disclosure includes apparatuses and methods for operating neural networks. An example apparatus includes a plurality of neural networks, wherein the plurality of neural networks are configured to receive a particular portion of data and wherein each of the plurality of neural networks are configured to operate on the particular portion of data during a particular time period to make a determination regarding a characteristic of the particular portion of data.Type: GrantFiled: December 6, 2021Date of Patent: September 26, 2023Assignee: Micron Technology, Inc.Inventor: Perry V. Lea
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Publication number: 20230236752Abstract: The present disclosure includes apparatuses and methods for data movement. An example apparatus includes a memory device that includes a plurality of subarrays of memory cells and sensing circuitry coupled to the plurality of subarrays. The sensing circuitry includes a sense amplifier and a compute component. The memory device also includes a plurality of subarray controllers. Each subarray controller of the plurality of subarray controllers is coupled to a respective subarray of the plurality of subarrays and is configured to direct performance of an operation with respect to data stored in the respective subarray of the plurality of subarrays. The memory device is configured to move a data value corresponding to a result of an operation with respect to data stored in a first subarray of the plurality of subarrays to a memory cell in a second subarray of the plurality of subarrays.Type: ApplicationFiled: March 23, 2023Publication date: July 27, 2023Inventors: Perry V. Lea, Glen E. Hush
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Patent number: 11693561Abstract: The present disclosure includes apparatuses and methods for simultaneous in data path compute operations. An apparatus can include a memory device having an array of memory cells and sensing circuitry selectably coupled to the array. A plurality of shared I/O lines can be configured to move data from the array of memory cells to a first portion of logic stripes and a second portion of logic stripes for in data path compute operations associated with the array. The first portion of logic stripes can perform a first number of operations on a first portion of data moved from the array of memory cells to the first portion of logic stripes while the second portion of logic stripes perform a second number of operations on a second portion of data moved from the array of memory cells to the second portion of logic stripes during a first time period.Type: GrantFiled: June 1, 2022Date of Patent: July 4, 2023Assignee: Micron Technology, Inc.Inventors: Perry V. Lea, Glen E. Hush
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Patent number: 11675538Abstract: An example apparatus includes a PIM capable device having an array of memory cells and sensing circuitry coupled to the array, where the sensing circuitry includes a sense amplifier and a compute component. The PIM capable device includes timing circuitry selectably coupled to the sensing circuitry. The timing circuitry is configured to control timing of performance of operations performed using the sensing circuitry. The PIM capable device also includes a sequencer selectably coupled to the timing circuitry. The sequencer is configured to coordinate compute operations. The apparatus also includes a source external to the PIM capable device. The sequencer is configured to receive a command instruction set from the source to initiate performance of a compute operation.Type: GrantFiled: May 24, 2021Date of Patent: June 13, 2023Assignee: Micron Technology, Inc.Inventors: Perry V. Lea, Timothy P. Finkbeiner
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Patent number: 11663137Abstract: An example memory array page table walk can include using an array of memory cells configured to store a page table. The page table walk can include using sensing circuitry coupled to the array. The page table walk can include using a controller coupled to the array. The controller can be configured to operate the sensing circuitry to determine a physical address of a portion of data by accessing the page table in the array of memory cells. The controller can be configured to operate the sensing circuitry to cause storing of the portion of data in a buffer.Type: GrantFiled: November 19, 2021Date of Patent: May 30, 2023Assignee: Micron Technology, Inc.Inventor: Perry V. Lea
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Patent number: 11664064Abstract: The present disclosure includes apparatuses and methods for performing operations by a memory device in a self-refresh state. An example includes an array of memory cells and a controller coupled to the array of memory cells. The controller is configured to direct performance of compute operations on data stored in the array when the array is in a self-refresh state.Type: GrantFiled: March 18, 2022Date of Patent: May 30, 2023Assignee: Micron Technology, Inc.Inventors: Perry V. Lea, Glen E. Hush
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Patent number: 11625336Abstract: The present disclosure is related to encryption of executables in computational memory. Computational memory can traverse an operating system page table in the computational memory for a page marked as executable. In response to finding a page marked as executable, the computational memory can determine whether the page marked as executable has been encrypted. In response to determining that the page marked as executable is not encrypted, the computational memory can generate a key for the page marked as executable. The computational memory can encrypt the page marked as executable using the key.Type: GrantFiled: June 22, 2020Date of Patent: April 11, 2023Assignee: Micron Technology, Inc.Inventor: Perry V. Lea
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Patent number: 11614878Abstract: The present disclosure includes apparatuses and methods for data movement. An example apparatus includes a memory device that includes a plurality of subarrays of memory cells and sensing circuitry coupled to the plurality of subarrays. The sensing circuitry includes a sense amplifier and a compute component. The memory device also includes a plurality of subarray controllers. Each subarray controller of the plurality of subarray controllers is coupled to a respective subarray of the plurality of subarrays and is configured to direct performance of an operation with respect to data stored in the respective subarray of the plurality of subarrays. The memory device is configured to move a data value corresponding to a result of an operation with respect to data stored in a first subarray of the plurality of subarrays to a memory cell in a second subarray of the plurality of subarrays.Type: GrantFiled: May 17, 2021Date of Patent: March 28, 2023Assignee: Micron Technology, Inc.Inventors: Perry V. Lea, Glen E. Hush
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Publication number: 20230070383Abstract: The present disclosure includes apparatuses and methods for bank to bank data transfer. An example apparatus includes a plurality of banks of memory cells, an internal bus configured to transfer data between the plurality of banks and an external bus interface, and a bank-to-bank transfer bus configured to transfer data between the plurality of banks.Type: ApplicationFiled: November 11, 2022Publication date: March 9, 2023Inventors: Perry V. Lea, Troy A. Manning
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Patent number: 11593200Abstract: Examples of the present disclosure provide apparatuses and methods for error code calculation. The apparatus can include an array of memory cells that are coupled to sense lines. The apparatus can include a controller configured to control a sensing circuitry, that is coupled to the sense lines, to perform a number of operations without transferring data via an input/output (I/O) lines. The sensing circuitry can be controlled to calculate an error code for data stored in the array of memory cells and compare the error code with an initial error code for the data to determine whether the data has been modified.Type: GrantFiled: May 23, 2022Date of Patent: February 28, 2023Assignee: Micron Technology, Inc.Inventors: Perry V. Lea, Timothy P. Finkbeiner
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Patent number: 11586389Abstract: Apparatuses and methods are provided for processing in memory. An example apparatus comprises a host and a processing in memory (PIM) capable device coupled to the host via an interface comprising a sideband channel. The PIM capable device comprises an array of memory cells coupled to sensing circuitry and is configured to perform bit vector operations on data stored in the array, and the host comprises a PIM control component to perform virtual address resolution for PIM operations prior to providing a number of corresponding bit vector operations to the PIM capable device via the sideband channel.Type: GrantFiled: November 1, 2021Date of Patent: February 21, 2023Assignee: Micron Technology, Inc.Inventors: Perry V. Lea, Timothy P. Finkbeiner
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Patent number: 11550742Abstract: The present disclosure includes apparatuses and methods for in data path compute operations. An example apparatus includes an array of memory cells. Sensing circuitry is selectably coupled to the array. A plurality of shared input/output (I/O) lines provides a data path. The plurality of shared I/O lines selectably couples a first subrow of a row of the array via the sensing circuitry to a first compute component in the data path to move a first data value from the first subrow to the first compute component and a second subrow of the respective row via the sensing circuitry to a second compute component to move a second data value from the second subrow to the second compute component. An operation is performed on the first data value from the first subrow using the first compute component substantially simultaneously with movement of the second data value from the second subrow to the second compute component.Type: GrantFiled: June 28, 2021Date of Patent: January 10, 2023Assignee: Micron Technology, Inc.Inventor: Perry V. Lea
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Patent number: 11514957Abstract: The present disclosure includes apparatuses and methods for bank to bank data transfer. An example apparatus includes a plurality of banks of memory cells, an internal bus configured to transfer data between the plurality of banks and an external bus interface, and a bank-to-bank transfer bus configured to transfer data between the plurality of banks.Type: GrantFiled: October 5, 2020Date of Patent: November 29, 2022Assignee: Micron Technology, Inc.Inventors: Perry V. Lea, Troy A. Manning
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Patent number: 11474965Abstract: The present disclosure includes apparatuses and methods for in-memory data switching networks. An example apparatus includes an array of memory cells. Sensing circuitry is selectably coupled to the array of memory cells. An input/output (I/O) line is shared as a data path for in-memory data switching associated with the array. An in-memory data switching network is selectably coupled to the respective shared I/O line. A controller is configured to couple to the in-memory data switching network and direct enablement of a switch protocol.Type: GrantFiled: November 16, 2020Date of Patent: October 18, 2022Assignee: Micron Technology, Inc.Inventor: Perry V. Lea
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Publication number: 20220291834Abstract: The present disclosure includes apparatuses and methods for simultaneous in data path compute operations. An apparatus can include a memory device having an array of memory cells and sensing circuitry selectably coupled to the array. A plurality of shared I/O lines can be configured to move data from the array of memory cells to a first portion of logic stripes and a second portion of logic stripes for in data path compute operations associated with the array. The first portion of logic stripes can perform a first number of operations on a first portion of data moved from the array of memory cells to the first portion of logic stripes while the second portion of logic stripes perform a second number of operations on a second portion of data moved from the array of memory cells to the second portion of logic stripes during a first time period.Type: ApplicationFiled: June 1, 2022Publication date: September 15, 2022Inventors: Perry V. Lea, Glen E. Hush
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Publication number: 20220283898Abstract: Examples of the present disclosure provide apparatuses and methods for error code calculation. The apparatus can include an array of memory cells that are coupled to sense lines. The apparatus can include a controller configured to control a sensing circuitry, that is coupled to the sense lines, to perform a number of operations without transferring data via an input/output (I/O) lines. The sensing circuitry can be controlled to calculate an error code for data stored in the array of memory cells and compare the error code with an initial error code for the data to determine whether the data has been modified.Type: ApplicationFiled: May 23, 2022Publication date: September 8, 2022Inventors: Perry V. Lea, Timothy P. Finkbeiner