Patents by Inventor Peruvemba S. Balasubramanian
Peruvemba S. Balasubramanian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 5610947Abstract: Biphase or FM encoding is combined with Flash modulation in infrared (IR) communication. By shrinking the coded pulse width in the modulation process, power dissipation is effectively reduced to the point where FM encoding can be advantageously adapted to IR communication in a synchronous communication system. Noise filtering is also described.Type: GrantFiled: October 14, 1994Date of Patent: March 11, 1997Assignee: International Business Machines CorporationInventors: Peruvemba S. Balasubramanian, Nathan J. Lee, Scott D. Lekuch
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Patent number: 5602873Abstract: A modulation scheme and system, compatible with both the asynchronous IRDA mode and the synchronous mode of IR communication, involves Non-Return-to-Zero-Inverted (NRZI) and Flash pulse encoding in conjunction with zero-bit stuffing. A digital data stream has a zero-bit inserted therein, before NRZI format encoding, whenever five consecutive one's are detected in the stream to enable the controller to distinguish the data from flags, which are exempt from the zero-bit insertion, and to provide enough transitions in the data so that the demodulator's digital phase lock loop can stay locked independent of the data contents. A Flash pulse (of from 3/16 to 8/16 of bit cell width, depending on the data rate) is generated whenever a transition is detected in the NRZI formatted data. The result, in keeping with IRDA modulation, is that a Flash pulse is generated whenever a zero occurs in the data stream.Type: GrantFiled: October 14, 1994Date of Patent: February 11, 1997Assignee: International Business Machines CorporationInventors: Peruvemba S. Balasubramanian, Nathan J. Lee, Scott D. Lekuch
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Patent number: 5566098Abstract: A pen-based computer including a housing and a flat display integral therewith. The flat display can display an image corresponding to text, data and graphic information in several orientations. A plurality of switches enables the user to select an orientation for the image relative to the orientation of the flat display. In one embodiment the switches are mercury switches positioned to automatically align the orientation of the image relative to motion of the flat panel display relative to the force of gravity. An optional additional switch resets the orientation of the image to a predetermined orientation or prevents the reorientation of the image responsive to the mercury switches.Type: GrantFiled: January 30, 1995Date of Patent: October 15, 1996Assignee: International Business Machines CorporationInventors: Samuel A. M. Lucente, Peruvemba S. Balasubramanian, Richard F. Sapper, Nathan J. Lee
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Patent number: 5557634Abstract: A directed infrared (IR) communication controller which supports interoperability among protocols and which can communicate at baud rates of up to 2.34 Mbps while supporting the IRDA standard as well as Sharp's 500 KHz ASK, NRZI, and Biphase modulated IR systems. A method for automatically determining which type of infrared signal is being received is also described.Type: GrantFiled: October 14, 1994Date of Patent: September 17, 1996Assignee: International Business Machines CorporationInventors: Peruvemba S. Balasubramanian, Nathan J. Lee, Scott D. Lekuch
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Patent number: 5532641Abstract: Amplitude Shift Keying (ASK) modulation system and method with an ASK demodulator that is implemented with an analog-emulating digital bandpass filter. The bandpass filter also generates a carrier detect signal when it detects a carrier frequency that passes the filter pass band.Type: GrantFiled: October 14, 1994Date of Patent: July 2, 1996Assignee: International Business Machines CorporationInventors: Peruvemba S. Balasubramanian, Nathan J. Lee, Scott D. Lekuch
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Patent number: 5432720Abstract: A pen-based computer includes a housing and a flat panel display integral therewith. The computer housing has a slanted parallelpiped configuration with polyhedron-shaped top and bottom surfaces and parallelogram-shaped side and end surfaces interconnecting the top and bottom surfaces. The side and end surfaces of the housing include one adjacent side and end surface having an upward exposure, and another adjacent side and end surface having a downward exposure, with each of the side and end surfaces extending at an angle of between about 10 and 45 degrees from the top surface to the bottom surface. The flat panel display for the computer is mounted proximate to the top surface of the housing proximate one corner, and the bottom surface of the housing is designed to be supported on a horizontal support surface.Type: GrantFiled: November 13, 1992Date of Patent: July 11, 1995Assignee: International Business Machines CorporationInventors: Samuel A. M. Lucente, Peruvemba S. Balasubramanian, Richard F. Sapper, Nathan J. Lee
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Patent number: 4177452Abstract: A write once, read only electrically programmable storage circuit is disclosed, which employs a flip-flop circuit to store the programmed conductive state of the array device, by means of a blocking transistor connected between the array device and one node of the flip-flop, the control electrode of the blocking transistor being connected to the other node of the flip-flop. With the flip-flop having an initial first state so that the blocking device is conductive, a precharged signal may be conducted through the array device to ground indicating a first stored information state. By driving a write signal through the array device and the blocking device, of sufficient magnitude to set the flip-flop in its opposite state, the blocking device is then made nonconductive and subsequent attempts to transmit a precharge signal through the array device to ground, will not be possible, indicating a second stored information state.Type: GrantFiled: June 5, 1978Date of Patent: December 4, 1979Assignee: International Business Machines CorporationInventors: Peruvemba S. Balasubramanian, Stephen B. Greenspan
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Patent number: 4140967Abstract: A merged AND/OR array PLA is disclosed wherein the merger is accomplished by forming the gates of the FET devices in the AND array by means of an upper conductor layer and the gates of the FET devices in the OR array, which are connected to the drain of the devices in the AND array, by means of lower level conductor layer, so that the devices are contiguous. The PLA structure uses a polysilicon layer for interconnection between AND array FET drains and OR array FET gates, with the AND array FETs or OR array FETs being intermixed in a single array. The OR array outputs are oriented vertically, alternating between the AND product terms and ground diffusions. All PLA outputs are oriented vertically within the same array.Type: GrantFiled: June 24, 1977Date of Patent: February 20, 1979Assignee: International Business Machines CorporationInventors: Peruvemba S. Balasubramanian, Claude R. Bertin, Stephen B. Greenspan
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Patent number: 4140921Abstract: An array of parallel FET load circuits on an IC (integrated circuit) chip can have their respective signal delays equalized where their nodal capacitances are different or alternately can have their signal delays set for different durations to meet the needs of a subsequent circuit, by adjusting the current driving capacity of a driver driving each circuit to meet the desired delay requirements thereof.Type: GrantFiled: August 31, 1977Date of Patent: February 20, 1979Assignee: International Business Machines CorporationInventors: Peruvemba S. Balasubramanian, Stephen B. Greenspan, Krishnamurthi Venkataraman
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Patent number: T977006Abstract: a read only memory on a semiconductor substrate having metal word lines and diffused bit lines with optimized dimensions for a selected performance and storage capacity with the metal lines being along an X dimension and the diffused lines being orthogonally related to the metal lines along a Y dimension. The X dimension for the substrate is given by the relation X = 2.sup.N .multidot. WL .multidot. K1 where 2.sup.N is an integer definitive of the number of words on a metal line where N is any integer power greater than zero; WL is word length which equals the number of storage devices per word selected for a word and K1 is a constant definitive of the average spacing in mils between the storage devices along the first length, and the Y dimension being given by a second relation Y = K2 .multidot. QN where K2 is a constant definitive of the spacing in mils between the adjacent rows of storage devices along the second length and Q is the number of said words.Type: GrantFiled: April 24, 1978Date of Patent: December 5, 1978Assignee: International Business Machines CorporationInventors: Peruvemba S. Balasubramanian, Edwin C. Grazier, John D. Henke, Robert P. Latham, Martin J. Myers